mirror of https://github.com/YosysHQ/yosys.git
044ca9dde4
This patch should support things like `define foo(a, b = 3, c) a+b+c `foo(1, ,2) which will evaluate to 1+3+2. It also spots mistakes like `foo(1) (the 3rd argument doesn't have a default value, so a call site is required to set it). Most of the patch is a simple parser for the format in preproc.cc, but I've also taken the opportunity to wrap up the "name -> definition" map in a type, rather than use multiple std::map's. Since this type needs to be visible to code that touches defines, I've pulled it (and the frontend_verilog_preproc declaration) out into a new file at frontends/verilog/preproc.h and included that where necessary. Finally, the patch adds a few tests in tests/various to check that we are parsing everything correctly. |
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| .. | ||
| bitpattern.h | ||
| calc.cc | ||
| cellaigs.cc | ||
| cellaigs.h | ||
| celledges.cc | ||
| celledges.h | ||
| celltypes.h | ||
| consteval.h | ||
| cost.h | ||
| driver.cc | ||
| hashlib.h | ||
| log.cc | ||
| log.h | ||
| macc.h | ||
| modtools.h | ||
| register.cc | ||
| register.h | ||
| rtlil.cc | ||
| rtlil.h | ||
| satgen.h | ||
| sigtools.h | ||
| timinginfo.h | ||
| utils.h | ||
| yosys.cc | ||
| yosys.h | ||