yosys/passes
Eddie Hung 3879ca1398 Do not require changes to cells_sim.v; try and work out comb model 2019-10-05 22:55:18 -07:00
..
cmds Add "check -allow-tbuf" 2019-10-03 11:49:56 +02:00
equiv Update doc for equiv_opt 2019-09-30 10:59:56 -07:00
fsm RTLIL::S{0,1} -> State::S{0,1} 2019-08-07 11:12:38 -07:00
hierarchy Adopt @cliffordwolf's suggestion 2019-09-03 12:18:50 -07:00
memory stoi -> atoi 2019-08-07 11:09:17 -07:00
opt Revert "SigSet<Cell*> to use stable compare class" 2019-09-13 09:49:15 -07:00
pmgen Fix xilinx_dsp for unsigned extensions 2019-10-04 16:46:15 -07:00
proc proc_clean: fix order of switch insertion. 2019-08-19 16:44:23 +00:00
sat Fix $dlatch handling in async2sync 2019-09-30 14:58:23 +02:00
techmap Do not require changes to cells_sim.v; try and work out comb model 2019-10-05 22:55:18 -07:00
tests Document (* gentb_skip *) attr for test_autotb 2019-09-18 12:41:35 -07:00