mirror of https://github.com/YosysHQ/yosys.git
23 lines
507 B
Plaintext
23 lines
507 B
Plaintext
#design should be loaded before executing
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#set the: hierarchy -top <module_top>
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#set the: hierarchy -libdir <dir>
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#high level synthesis
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#################
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#converting processes to cells
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proc;
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opt; opt_const -mux_undef; opt;
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rename -hide;;;
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#converting pmux to mux
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techmap -map techlibs/common/pmux2mux.v;;
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memory -nomap;;
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#flatten design
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flatten;;
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#converting asyn memory write to syn memory
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memory_unpack;
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#cell output to be a single wire
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splitnets -driver;
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opt;;;
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#writing btor
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write_btor design.btor;
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