mirror of https://github.com/YosysHQ/yosys.git
116 lines
3.5 KiB
C++
116 lines
3.5 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/register.h"
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#include "kernel/sigtools.h"
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#include "kernel/log.h"
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#include <stdlib.h>
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#include <stdio.h>
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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void proc_get_const(RTLIL::SigSpec &sig, RTLIL::CaseRule &rule)
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{
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log_assert(rule.compare.size() == 0);
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while (1) {
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RTLIL::SigSpec tmp = sig;
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for (auto &it : rule.actions)
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tmp.replace(it.first, it.second);
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if (tmp == sig)
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break;
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sig = tmp;
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}
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}
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void proc_init(RTLIL::Module *mod, RTLIL::Process *proc)
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{
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bool found_init = false;
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for (auto &sync : proc->syncs)
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if (sync->type == RTLIL::SyncType::STi)
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{
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found_init = true;
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log("Found init rule in `%s.%s'.\n", mod->name.c_str(), proc->name.c_str());
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for (auto &action : sync->actions)
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{
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RTLIL::SigSpec lhs = action.first;
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RTLIL::SigSpec rhs = action.second;
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proc_get_const(rhs, proc->root_case);
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if (!rhs.is_fully_const())
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log_cmd_error("Failed to get a constant init value for %s: %s\n", log_signal(lhs), log_signal(rhs));
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int offset = 0;
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for (auto &lhs_c : lhs.chunks()) {
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if (lhs_c.wire != NULL) {
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RTLIL::SigSpec value = rhs.extract(offset, lhs_c.width);
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if (value.size() != lhs_c.wire->width)
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log_cmd_error("Init value is not for the entire wire: %s = %s\n", log_signal(lhs_c), log_signal(value));
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log(" Setting init value: %s = %s\n", log_signal(lhs_c.wire), log_signal(value));
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lhs_c.wire->attributes["\\init"] = value.as_const();
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}
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offset += lhs_c.width;
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}
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}
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}
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if (found_init) {
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std::vector<RTLIL::SyncRule*> new_syncs;
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for (auto &sync : proc->syncs)
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if (sync->type == RTLIL::SyncType::STi)
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delete sync;
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else
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new_syncs.push_back(sync);
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proc->syncs.swap(new_syncs);
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}
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}
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struct ProcInitPass : public Pass {
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ProcInitPass() : Pass("proc_init", "convert initial block to init attributes") { }
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virtual void help()
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" proc_init [selection]\n");
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log("\n");
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log("This pass extracts the 'init' actions from processes (generated from Verilog\n");
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log("'initial' blocks) and sets the initial value to the 'init' attribute on the\n");
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log("respective wire.\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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log_header("Executing PROC_INIT pass (extract init attributes).\n");
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extra_args(args, 1, design);
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for (auto mod : design->modules())
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if (design->selected(mod))
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for (auto &proc_it : mod->processes)
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if (design->selected(mod, proc_it.second))
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proc_init(mod, proc_it.second);
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}
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} ProcInitPass;
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PRIVATE_NAMESPACE_END
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