mirror of https://github.com/YosysHQ/yosys.git
410 lines
10 KiB
C++
410 lines
10 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#ifndef MODTOOLS_H
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#define MODTOOLS_H
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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#include "kernel/celltypes.h"
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YOSYS_NAMESPACE_BEGIN
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struct ModIndex : public RTLIL::Monitor
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{
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struct PortInfo {
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const RTLIL::Cell* cell;
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const RTLIL::IdString &port;
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const int offset;
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PortInfo(RTLIL::Cell* _c, const RTLIL::IdString &_p, int _o) : cell(_c), port(_p), offset(_o) { }
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bool operator<(const PortInfo &other) const {
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if (cell != other.cell)
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return cell < other.cell;
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if (offset != other.offset)
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return offset < other.offset;
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return port < other.port;
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}
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};
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struct SigBitInfo
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{
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bool is_input, is_output;
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std::set<PortInfo> ports;
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SigBitInfo() : is_input(false), is_output(false) { }
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};
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SigMap sigmap;
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RTLIL::Module *module;
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std::map<RTLIL::SigBit, SigBitInfo> database;
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bool auto_reload_module;
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void port_add(RTLIL::Cell *cell, const RTLIL::IdString &port, const RTLIL::SigSpec &sig)
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{
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for (int i = 0; i < SIZE(sig); i++)
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database[sigmap(sig[i])].ports.insert(PortInfo(cell, port, i));
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}
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void port_del(RTLIL::Cell *cell, const RTLIL::IdString &port, const RTLIL::SigSpec &sig)
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{
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for (int i = 0; i < SIZE(sig); i++)
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database[sigmap(sig[i])].ports.erase(PortInfo(cell, port, i));
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}
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const SigBitInfo &info(RTLIL::SigBit bit)
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{
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return database[sigmap(bit)];
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}
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void reload_module()
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{
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sigmap.clear();
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sigmap.set(module);
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database.clear();
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for (auto wire : module->wires())
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if (wire->port_input || wire->port_output)
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for (int i = 0; i < SIZE(wire); i++) {
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if (wire->port_input)
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database[sigmap(RTLIL::SigBit(wire, i))].is_input = true;
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if (wire->port_output)
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database[sigmap(RTLIL::SigBit(wire, i))].is_output = true;
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}
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for (auto cell : module->cells())
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for (auto &conn : cell->connections())
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port_add(cell, conn.first, conn.second);
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auto_reload_module = false;
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}
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virtual void notify_connect(RTLIL::Cell *cell, const RTLIL::IdString &port, const RTLIL::SigSpec &old_sig, RTLIL::SigSpec &sig) override
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{
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if (auto_reload_module)
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reload_module();
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port_del(cell, port, old_sig);
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port_add(cell, port, sig);
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}
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virtual void notify_connect(RTLIL::Module *mod, const RTLIL::SigSig&)
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{
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log_assert(module == mod);
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auto_reload_module = true;
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}
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virtual void notify_connect(RTLIL::Module *mod, const std::vector<RTLIL::SigSig>&)
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{
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log_assert(module == mod);
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auto_reload_module = true;
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}
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virtual void notify_blackout(RTLIL::Module *mod)
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{
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log_assert(module == mod);
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auto_reload_module = true;
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}
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ModIndex(RTLIL::Module *_m) : module(_m) {
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auto_reload_module = true;
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module->monitors.insert(this);
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}
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~ModIndex() {
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module->monitors.erase(this);
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}
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};
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struct ModWalker
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{
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struct PortBit
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{
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RTLIL::Cell *cell;
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RTLIL::IdString port;
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int offset;
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bool operator<(const PortBit &other) const {
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if (cell != other.cell)
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return cell < other.cell;
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if (port != other.port)
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return port < other.port;
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return offset < other.offset;
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}
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};
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RTLIL::Design *design;
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RTLIL::Module *module;
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CellTypes ct;
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SigMap sigmap;
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std::map<RTLIL::SigBit, std::set<PortBit>> signal_drivers;
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std::map<RTLIL::SigBit, std::set<PortBit>> signal_consumers;
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std::set<RTLIL::SigBit> signal_inputs, signal_outputs;
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std::map<RTLIL::Cell*, std::set<RTLIL::SigBit>> cell_outputs, cell_inputs;
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void add_wire(RTLIL::Wire *wire)
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{
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if (wire->port_input) {
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std::vector<RTLIL::SigBit> bits = sigmap(wire);
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for (auto bit : bits)
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if (bit.wire != NULL)
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signal_inputs.insert(bit);
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}
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if (wire->port_output) {
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std::vector<RTLIL::SigBit> bits = sigmap(wire);
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for (auto bit : bits)
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if (bit.wire != NULL)
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signal_outputs.insert(bit);
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}
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}
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void add_cell_port(RTLIL::Cell *cell, RTLIL::IdString port, std::vector<RTLIL::SigBit> bits, bool is_output, bool is_input)
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{
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for (int i = 0; i < int(bits.size()); i++)
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if (bits[i].wire != NULL) {
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PortBit pbit = { cell, port, i };
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if (is_output) {
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signal_drivers[bits[i]].insert(pbit);
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cell_outputs[cell].insert(bits[i]);
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}
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if (is_input) {
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signal_consumers[bits[i]].insert(pbit);
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cell_inputs[cell].insert(bits[i]);
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}
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}
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}
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void add_cell(RTLIL::Cell *cell)
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{
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if (ct.cell_known(cell->type)) {
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for (auto &conn : cell->connections())
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add_cell_port(cell, conn.first, sigmap(conn.second),
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ct.cell_output(cell->type, conn.first),
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ct.cell_input(cell->type, conn.first));
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} else {
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for (auto &conn : cell->connections())
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add_cell_port(cell, conn.first, sigmap(conn.second), true, true);
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}
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}
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ModWalker() : design(NULL), module(NULL)
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{
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}
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ModWalker(RTLIL::Design *design, RTLIL::Module *module, CellTypes *filter_ct = NULL)
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{
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setup(design, module, filter_ct);
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}
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void setup(RTLIL::Design *design, RTLIL::Module *module, CellTypes *filter_ct = NULL)
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{
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this->design = design;
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this->module = module;
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ct.clear();
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ct.setup(design);
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sigmap.set(module);
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signal_drivers.clear();
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signal_consumers.clear();
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signal_inputs.clear();
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signal_outputs.clear();
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for (auto &it : module->wires_)
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add_wire(it.second);
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for (auto &it : module->cells_)
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if (filter_ct == NULL || filter_ct->cell_known(it.second->type))
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add_cell(it.second);
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}
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// get_* methods -- single RTLIL::SigBit
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template<typename T>
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inline bool get_drivers(std::set<PortBit> &result, RTLIL::SigBit bit) const
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{
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bool found = false;
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if (signal_drivers.count(bit)) {
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const std::set<PortBit> &r = signal_drivers.at(bit);
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result.insert(r.begin(), r.end());
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found = true;
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}
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return found;
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}
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template<typename T>
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inline bool get_consumers(std::set<PortBit> &result, RTLIL::SigBit bit) const
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{
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bool found = false;
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if (signal_consumers.count(bit)) {
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const std::set<PortBit> &r = signal_consumers.at(bit);
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result.insert(r.begin(), r.end());
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found = true;
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}
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return found;
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}
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template<typename T>
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inline bool get_inputs(std::set<RTLIL::SigBit> &result, RTLIL::SigBit bit) const
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{
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bool found = false;
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if (signal_inputs.count(bit))
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result.insert(bit), found = true;
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return found;
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}
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template<typename T>
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inline bool get_outputs(std::set<RTLIL::SigBit> &result, RTLIL::SigBit bit) const
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{
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bool found = false;
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if (signal_outputs.count(bit))
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result.insert(bit), found = true;
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return found;
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}
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// get_* methods -- container of RTLIL::SigBit's (always by reference)
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template<typename T>
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inline bool get_drivers(std::set<PortBit> &result, const T &bits) const
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{
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bool found = false;
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for (RTLIL::SigBit bit : bits)
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if (signal_drivers.count(bit)) {
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const std::set<PortBit> &r = signal_drivers.at(bit);
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result.insert(r.begin(), r.end());
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found = true;
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}
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return found;
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}
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template<typename T>
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inline bool get_consumers(std::set<PortBit> &result, const T &bits) const
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{
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bool found = false;
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for (RTLIL::SigBit bit : bits)
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if (signal_consumers.count(bit)) {
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const std::set<PortBit> &r = signal_consumers.at(bit);
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result.insert(r.begin(), r.end());
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found = true;
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}
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return found;
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}
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template<typename T>
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inline bool get_inputs(std::set<RTLIL::SigBit> &result, const T &bits) const
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{
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bool found = false;
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for (RTLIL::SigBit bit : bits)
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if (signal_inputs.count(bit))
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result.insert(bit), found = true;
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return found;
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}
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template<typename T>
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inline bool get_outputs(std::set<RTLIL::SigBit> &result, const T &bits) const
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{
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bool found = false;
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for (RTLIL::SigBit bit : bits)
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if (signal_outputs.count(bit))
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result.insert(bit), found = true;
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return found;
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}
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// get_* methods -- call by RTLIL::SigSpec (always by value)
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bool get_drivers(std::set<PortBit> &result, RTLIL::SigSpec signal) const
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{
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std::vector<RTLIL::SigBit> bits = sigmap(signal);
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return get_drivers(result, bits);
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}
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bool get_consumers(std::set<PortBit> &result, RTLIL::SigSpec signal) const
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{
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std::vector<RTLIL::SigBit> bits = sigmap(signal);
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return get_consumers(result, bits);
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}
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bool get_inputs(std::set<RTLIL::SigBit> &result, RTLIL::SigSpec signal) const
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{
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std::vector<RTLIL::SigBit> bits = sigmap(signal);
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return get_inputs(result, bits);
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}
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bool get_outputs(std::set<RTLIL::SigBit> &result, RTLIL::SigSpec signal) const
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{
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std::vector<RTLIL::SigBit> bits = sigmap(signal);
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return get_outputs(result, bits);
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}
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// has_* methods -- call by reference
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template<typename T>
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inline bool has_drivers(const T &sig) const {
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std::set<PortBit> result;
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return get_drivers(result, sig);
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}
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template<typename T>
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inline bool has_consumers(const T &sig) const {
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std::set<PortBit> result;
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return get_consumers(result, sig);
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}
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template<typename T>
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inline bool has_inputs(const T &sig) const {
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std::set<RTLIL::SigBit> result;
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return get_inputs(result, sig);
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}
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template<typename T>
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inline bool has_outputs(const T &sig) const {
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std::set<RTLIL::SigBit> result;
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return get_outputs(result, sig);
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}
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// has_* methods -- call by value
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inline bool has_drivers(RTLIL::SigSpec sig) const {
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std::set<PortBit> result;
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return get_drivers(result, sig);
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}
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inline bool has_consumers(RTLIL::SigSpec sig) const {
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std::set<PortBit> result;
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return get_consumers(result, sig);
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}
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inline bool has_inputs(RTLIL::SigSpec sig) const {
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std::set<RTLIL::SigBit> result;
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return get_inputs(result, sig);
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}
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inline bool has_outputs(RTLIL::SigSpec sig) const {
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std::set<RTLIL::SigBit> result;
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return get_outputs(result, sig);
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}
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};
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YOSYS_NAMESPACE_END
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#endif
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