mirror of https://github.com/YosysHQ/yosys.git
95 lines
1.9 KiB
Verilog
95 lines
1.9 KiB
Verilog
module abc9_test001(input a, output o);
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assign o = a;
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endmodule
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module abc9_test002(input [1:0] a, output o);
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assign o = a[1];
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endmodule
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module abc9_test003(input [1:0] a, output [1:0] o);
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assign o = a;
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endmodule
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module abc9_test004(input [1:0] a, output o);
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assign o = ^a;
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endmodule
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module abc9_test005(input [1:0] a, output o, output p);
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assign o = ^a;
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assign p = ~o;
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endmodule
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module abc9_test006(input [1:0] a, output [2:0] o);
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assign o[0] = ^a;
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assign o[1] = ~o[0];
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assign o[2] = o[1];
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endmodule
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module abc9_test007(input a, output o);
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wire b, c;
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assign c = ~a;
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assign b = c;
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abc9_test007_sub s(b, o);
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endmodule
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module abc9_test007_sub(input a, output b);
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assign b = a;
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endmodule
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module abc9_test008(input a, output o);
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wire b, c;
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assign b = ~a;
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assign c = b;
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abc9_test008_sub s(b, o);
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endmodule
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module abc9_test008_sub(input a, output b);
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assign b = ~a;
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endmodule
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// TODO
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//module abc9_test009(inout io, input oe);
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//reg latch;
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//always @(io or oe)
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// if (!oe)
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// latch <= io;
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//assign io = oe ? ~latch : 1'bz;
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//endmodule
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// TODO
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//module abc9_test010(inout [7:0] io, input oe);
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//reg [7:0] latch;
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//always @(io or oe)
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// if (!oe)
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// latch <= io;
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//assign io = oe ? ~latch : 1'bz;
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//endmodule
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// TODO
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//module abc9_test011(inout [7:0] io, input oe);
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//reg [7:0] latch;
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//always @(io or oe)
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// if (!oe)
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// latch[3:0] <= io;
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// else
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// latch[7:4] <= io;
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//assign io[3:0] = oe ? ~latch[3:0] : 4'bz;
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//assign io[7:4] = !oe ? {latch[4], latch[7:3]} : 4'bz;
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//endmodule
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// TODO
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//module abc9_test012(inout [7:0] io, input oe);
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//abc9_test012_sub sub(io, oe);
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//endmodule
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//
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//module abc9_test012_sub(inout [7:0] io, input oe);
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//reg [7:0] latch;
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//always @(io or oe)
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// if (!oe)
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// latch[3:0] <= io;
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// else
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// latch[7:4] <= io;
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//assign io[3:0] = oe ? ~latch[3:0] : 4'bz;
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//assign io[7:4] = !oe ? {latch[4], latch[7:3]} : 4'bz;
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//endmodule
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