mirror of https://github.com/YosysHQ/yosys.git
94 lines
2.5 KiB
Verilog
94 lines
2.5 KiB
Verilog
module $__NX_RAM_ (...);
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parameter INIT = 0;
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parameter OPTION_STD_MODE = "";
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parameter WIDTH = 24;
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parameter PORT_A_CLK_POL = 1;
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input PORT_A_CLK;
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input PORT_A_CLK_EN;
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input PORT_A_WR_EN;
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input [15:0] PORT_A_ADDR;
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input [WIDTH-1:0] PORT_A_WR_DATA;
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wire [24-1:0] A_DATA;
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output [WIDTH-1:0] PORT_A_RD_DATA;
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parameter PORT_B_CLK_POL = 1;
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input PORT_B_CLK;
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input PORT_B_CLK_EN;
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input PORT_B_WR_EN;
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input [15:0] PORT_B_ADDR;
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input [WIDTH-1:0] PORT_B_WR_DATA;
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wire [24-1:0] B_DATA;
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output [WIDTH-1:0] PORT_B_RD_DATA;
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generate
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if (OPTION_STD_MODE == "NOECC_48kx1") begin
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assign A_DATA = {24{PORT_A_WR_DATA[WIDTH-1:0]}};
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assign B_DATA = {24{PORT_B_WR_DATA[WIDTH-1:0]}};
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end
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else if (OPTION_STD_MODE == "NOECC_24kx2") begin
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assign A_DATA = {12{PORT_A_WR_DATA[WIDTH-1:0]}};
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assign B_DATA = {12{PORT_B_WR_DATA[WIDTH-1:0]}};
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end
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else if (OPTION_STD_MODE == "NOECC_16kx3") begin
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assign A_DATA = {8{PORT_A_WR_DATA[WIDTH-1:0]}};
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assign B_DATA = {8{PORT_B_WR_DATA[WIDTH-1:0]}};
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end
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else if (OPTION_STD_MODE == "NOECC_12kx4") begin
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assign A_DATA = {6{PORT_A_WR_DATA[WIDTH-1:0]}};
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assign B_DATA = {6{PORT_B_WR_DATA[WIDTH-1:0]}};
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end
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else if (OPTION_STD_MODE == "NOECC_8kx6") begin
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assign A_DATA = {4{PORT_A_WR_DATA[WIDTH-1:0]}};
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assign B_DATA = {4{PORT_B_WR_DATA[WIDTH-1:0]}};
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end
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else if (OPTION_STD_MODE == "NOECC_6kx8") begin
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assign A_DATA = {3{PORT_A_WR_DATA[WIDTH-1:0]}};
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assign B_DATA = {3{PORT_B_WR_DATA[WIDTH-1:0]}};
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end
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else if (OPTION_STD_MODE == "NOECC_4kx12") begin
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assign A_DATA = {2{PORT_A_WR_DATA[WIDTH-1:0]}};
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assign B_DATA = {2{PORT_B_WR_DATA[WIDTH-1:0]}};
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end
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else if (OPTION_STD_MODE == "NOECC_2kx24") begin
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assign A_DATA = PORT_A_WR_DATA;
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assign B_DATA = PORT_B_WR_DATA;
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end
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endgenerate
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NX_RAM_WRAP #(
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.std_mode(OPTION_STD_MODE),
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.mcka_edge(PORT_A_CLK_POL == 1 ? 1'b0 : 1'b1),
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.mckb_edge(PORT_B_CLK_POL == 1 ? 1'b0 : 1'b1),
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) _TECHMAP_REPLACE_ (
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.ACK(PORT_A_CLK),
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//.ACKS(PORT_A_CLK),
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//.ACKD(), // Not used in Non-ECC modes
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//.ACKR(),
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//.AR(),
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//.ACOR(),
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//.AERR(),
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.ACS(PORT_A_CLK_EN),
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.AWE(PORT_A_WR_EN),
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.AA(PORT_A_ADDR),
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.AI(A_DATA),
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.AO(PORT_A_RD_DATA),
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.BCK(PORT_B_CLK),
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//.BCKC(PORT_B_CLK),
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//.BCKD(), // Not used in Non-ECC modes
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//.BCKR()
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//.BR(),
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//.BCOR(),
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//.BERR(),
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.BCS(PORT_B_CLK_EN),
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.BWE(PORT_B_WR_EN),
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.BA(B_DATA),
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.BI(PORT_B_WR_DATA),
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.BO(PORT_B_RD_DATA)
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);
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endmodule |