| .. |
|
Makefile.inc
|
Add RF initialization
|
2024-08-15 17:50:36 +02:00 |
|
arith_map.v
|
fix co on nx_cy
|
2024-08-15 17:50:36 +02:00 |
|
brams.txt
|
block ram mapping for standard modes
|
2024-08-15 17:50:36 +02:00 |
|
brams_map.v
|
block ram mapping for standard modes
|
2024-08-15 17:50:36 +02:00 |
|
cells_bb.v
|
block ram mapping for standard modes
|
2024-08-15 17:50:36 +02:00 |
|
cells_bb_l.v
|
IOM
|
2024-08-15 17:50:36 +02:00 |
|
cells_bb_m.v
|
IOM
|
2024-08-15 17:50:36 +02:00 |
|
cells_bb_u.v
|
Split sim models into multiple files and implement few
|
2024-08-15 17:50:36 +02:00 |
|
cells_map.v
|
enable dff context initialization
|
2024-08-15 17:50:36 +02:00 |
|
cells_sim.v
|
Split sim models into multiple files and implement few
|
2024-08-15 17:50:36 +02:00 |
|
cells_sim_l.v
|
Split sim models into multiple files and implement few
|
2024-08-15 17:50:36 +02:00 |
|
cells_sim_m.v
|
Split sim models into multiple files and implement few
|
2024-08-15 17:50:36 +02:00 |
|
cells_sim_u.v
|
Split sim models into multiple files and implement few
|
2024-08-15 17:50:36 +02:00 |
|
cells_wrap.v
|
RAM
|
2024-08-15 17:50:36 +02:00 |
|
cells_wrap_l.v
|
IOM
|
2024-08-15 17:50:36 +02:00 |
|
cells_wrap_m.v
|
IOM
|
2024-08-15 17:50:36 +02:00 |
|
cells_wrap_u.v
|
Cleanup not connected ports
|
2024-08-15 17:50:36 +02:00 |
|
io_map.v
|
support other I/O configurations
|
2024-08-15 17:50:36 +02:00 |
|
latches_map.v
|
add latch mapping, and remove aldff for now
|
2024-08-15 17:50:36 +02:00 |
|
nx_carry.cc
|
remove debug attribute
|
2024-08-15 17:50:36 +02:00 |
|
rf_init.vh
|
Add RF initialization
|
2024-08-15 17:50:36 +02:00 |
|
rf_rams_l.txt
|
added no-rw-check, and new rfb models
|
2024-08-15 17:50:36 +02:00 |
|
rf_rams_m.txt
|
added no-rw-check, and new rfb models
|
2024-08-15 17:50:36 +02:00 |
|
rf_rams_map_l.v
|
added no-rw-check, and new rfb models
|
2024-08-15 17:50:36 +02:00 |
|
rf_rams_map_m.v
|
added no-rw-check, and new rfb models
|
2024-08-15 17:50:36 +02:00 |
|
rf_rams_map_u.v
|
Add RF initialization
|
2024-08-15 17:50:36 +02:00 |
|
rf_rams_u.txt
|
Add register file mapping
|
2024-08-15 17:50:36 +02:00 |
|
synth_nanoxplore.cc
|
Split sim models into multiple files and implement few
|
2024-08-15 17:50:36 +02:00 |
8eb099c1f4