mirror of https://github.com/YosysHQ/yosys.git
53 lines
1.6 KiB
C++
53 lines
1.6 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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* Eddie Hung <eddie@fpgeh.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#ifndef ABC_AIGERPARSE
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#define ABC_AIGERPARSE
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#include "kernel/yosys.h"
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YOSYS_NAMESPACE_BEGIN
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struct AigerReader
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{
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RTLIL::Design *design;
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std::istream &f;
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RTLIL::IdString clk_name;
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RTLIL::Module *module;
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unsigned M, I, L, O, A;
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unsigned B, C, J, F; // Optional in AIGER 1.9
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unsigned line_count;
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std::vector<RTLIL::Wire*> inputs;
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std::vector<RTLIL::Wire*> latches;
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std::vector<RTLIL::Wire*> outputs;
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std::vector<RTLIL::Wire*> bad_properties;
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AigerReader(RTLIL::Design *design, std::istream &f, RTLIL::IdString module_name, RTLIL::IdString clk_name);
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void parse_aiger();
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void parse_aiger_ascii();
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void parse_aiger_binary();
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};
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YOSYS_NAMESPACE_END
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#endif
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