mirror of https://github.com/YosysHQ/yosys.git
104 lines
4.9 KiB
ReStructuredText
104 lines
4.9 KiB
ReStructuredText
The ABC toolbox
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---------------
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.. role:: yoscrypt(code)
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:language: yoscrypt
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ABC_, from the University of California, Berkeley, is a logic toolbox used for
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fine-grained optimisation and LUT mapping.
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Yosys has two different commands, which both use this logic toolbox, but use it
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in different ways.
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The :cmd:ref:`abc` pass can be used for both ASIC (e.g. :yoscrypt:`abc
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-liberty`) and FPGA (:yoscrypt:`abc -lut`) mapping, but this page will focus on
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FPGA mapping.
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The :cmd:ref:`abc9` pass generally provides superior mapping quality due to
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being aware of combination boxes and DFF and LUT timings, giving it a more
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global view of the mapping problem.
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.. _ABC: https://github.com/berkeley-abc/abc
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ABC: the unit delay model, simple and efficient
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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The :cmd:ref:`abc` pass uses a highly simplified view of an FPGA:
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- An FPGA is made up of a network of inputs that connect through LUTs to a
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network of outputs. These inputs may actually be I/O pins, D flip-flops,
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memory blocks or DSPs, but ABC is unaware of this.
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- Each LUT has 1 unit of delay between an input and its output, and this applies
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for all inputs of a LUT, and for all sizes of LUT up to the maximum LUT size
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allowed; e.g. the delay between the input of a LUT2 and its output is the same
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as the delay between the input of a LUT6 and its output.
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- A LUT may take up a variable number of area units. This is constant for each
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size of LUT; e.g. a LUT4 may take up 1 unit of area, but a LUT5 may take up 2
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units of area, but this applies for all LUT4s and LUT5s.
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This is known as the "unit delay model", because each LUT uses one unit of
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delay.
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From this view, the problem ABC has to solve is finding a mapping of the network
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to LUTs that has the lowest delay, and then optimising the mapping for size
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while maintaining this delay.
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This approach has advantages:
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- It is simple and easy to implement.
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- Working with unit delays is fast to manipulate.
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- It reflects *some* FPGA families, for example, the iCE40HX/LP fits the
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assumptions of the unit delay model quite well (almost all synchronous blocks,
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except for adders).
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But this approach has drawbacks, too:
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- The network of inputs and outputs with only LUTs means that a lot of
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combinational cells (multipliers and LUTRAM) are invisible to the unit delay
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model, meaning the critical path it optimises for is not necessarily the
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actual critical path.
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- LUTs are implemented as multiplexer trees, so there is a delay caused by the
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result propagating through the remaining multiplexers. This means the
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assumption of delay being equal isn't true in physical hardware, and is
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proportionally larger for larger LUTs.
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- Even synchronous blocks have arrival times (propagation delay between clock
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edge to output changing) and setup times (requirement for input to be stable
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before clock edge) which affect the delay of a path.
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ABC9: the generalised delay model, realistic and flexible
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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ABC9 uses a more detailed and accurate model of an FPGA:
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- An FPGA is made up of a network of inputs that connect through LUTs and
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combinational boxes to a network of outputs. These boxes have specified delays
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between inputs and outputs, and may have an associated network ("white boxes")
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or not ("black boxes"), but must be treated as a whole.
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- Each LUT has a specified delay between an input and its output in arbitrary
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delay units, and this varies for all inputs of a LUT and for all sizes of LUT,
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but each size of LUT has the same associated delay; e.g. the delay between
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input A and output is different between a LUT2 and a LUT6, but is constant for
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all LUT6s.
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- A LUT may take up a variable number of area units. This is constant for each
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size of LUT; e.g. a LUT4 may take up 1 unit of area, but a LUT5 may take up 2
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units of area, but this applies for all LUT4s and LUT5s.
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This is known as the "generalised delay model", because it has been generalised
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to arbitrary delay units. ABC9 doesn't actually care what units you use here,
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but the Yosys convention is picoseconds. Note the introduction of boxes as a
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concept. While the generalised delay model does not require boxes, they
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naturally fit into it to represent combinational delays. Even synchronous delays
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like arrival and setup can be emulated with combinational boxes that act as a
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delay. This is further extended to white boxes, where the mapper is able to see
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inside a box, and remove orphan boxes with no outputs, such as adders.
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Again, ABC9 finds a mapping of the network to LUTs that has the lowest delay,
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and then minimises it to find the lowest area, but it has a lot more information
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to work with about the network.
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The result here is that ABC9 can remove boxes (like adders) to reduce area,
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optimise better around those boxes, and also permute inputs to give the critical
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path the fastest inputs.
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.. todo:: more about logic minimization & register balancing et al with ABC
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