mirror of https://github.com/YosysHQ/yosys.git
143 lines
4.1 KiB
C++
143 lines
4.1 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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* Copyright (C) 2018 David Shah <dave@ds0.me>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct Dff2dffsPass : public Pass {
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Dff2dffsPass() : Pass("dff2dffs", "process sync set/reset with SR over CE priority") { }
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void help() YS_OVERRIDE
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{
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log("\n");
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log(" dff2dffs [options] [selection]\n");
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log("\n");
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log("Merge synchronous set/reset $_MUX_ cells to create $__DFFS_[NP][NP][01], to be run before\n");
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log("dff2dffe for SR over CE priority.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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{
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log_header(design, "Executing dff2dffs pass (merge synchronous set/reset into FF cells).\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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// if (args[argidx] == "-singleton") {
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// singleton_mode = true;
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// continue;
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// }
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break;
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}
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extra_args(args, argidx, design);
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pool<IdString> dff_types;
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dff_types.insert(ID($_DFF_N_));
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dff_types.insert(ID($_DFF_P_));
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for (auto module : design->selected_modules())
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{
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log("Merging set/reset $_MUX_ cells into DFFs in %s.\n", log_id(module));
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SigMap sigmap(module);
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dict<SigBit, Cell*> sr_muxes;
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vector<Cell*> ff_cells;
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for (auto cell : module->selected_cells())
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{
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if (dff_types.count(cell->type)) {
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ff_cells.push_back(cell);
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continue;
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}
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if (cell->type != ID($_MUX_))
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continue;
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SigBit bit_a = sigmap(cell->getPort(ID::A));
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SigBit bit_b = sigmap(cell->getPort(ID::B));
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if (bit_a.wire == nullptr || bit_b.wire == nullptr)
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sr_muxes[sigmap(cell->getPort(ID::Y))] = cell;
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}
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for (auto cell : ff_cells)
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{
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SigSpec sig_d = cell->getPort(ID(D));
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if (GetSize(sig_d) < 1)
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continue;
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SigBit bit_d = sigmap(sig_d[0]);
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if (sr_muxes.count(bit_d) == 0)
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continue;
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Cell *mux_cell = sr_muxes.at(bit_d);
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SigBit bit_a = sigmap(mux_cell->getPort(ID::A));
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SigBit bit_b = sigmap(mux_cell->getPort(ID::B));
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SigBit bit_s = sigmap(mux_cell->getPort(ID(S)));
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log(" Merging %s (A=%s, B=%s, S=%s) into %s (%s).\n", log_id(mux_cell),
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log_signal(bit_a), log_signal(bit_b), log_signal(bit_s), log_id(cell), log_id(cell->type));
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SigBit sr_val, sr_sig;
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bool invert_sr;
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sr_sig = bit_s;
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if (bit_a.wire == nullptr) {
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bit_d = bit_b;
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sr_val = bit_a;
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invert_sr = true;
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} else {
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log_assert(bit_b.wire == nullptr);
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bit_d = bit_a;
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sr_val = bit_b;
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invert_sr = false;
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}
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if (sr_val == State::S1) {
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if (cell->type == ID($_DFF_N_)) {
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if (invert_sr) cell->type = ID($__DFFS_NN1_);
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else cell->type = ID($__DFFS_NP1_);
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} else {
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log_assert(cell->type == ID($_DFF_P_));
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if (invert_sr) cell->type = ID($__DFFS_PN1_);
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else cell->type = ID($__DFFS_PP1_);
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}
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} else {
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if (cell->type == ID($_DFF_N_)) {
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if (invert_sr) cell->type = ID($__DFFS_NN0_);
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else cell->type = ID($__DFFS_NP0_);
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} else {
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log_assert(cell->type == ID($_DFF_P_));
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if (invert_sr) cell->type = ID($__DFFS_PN0_);
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else cell->type = ID($__DFFS_PP0_);
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}
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}
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cell->setPort(ID(R), sr_sig);
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cell->setPort(ID(D), bit_d);
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}
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}
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}
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} Dff2dffsPass;
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PRIVATE_NAMESPACE_END
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