mirror of https://github.com/YosysHQ/yosys.git
34 lines
562 B
Verilog
34 lines
562 B
Verilog
module counter_tb;
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/* Make a reset pulse and specify dump file */
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reg reset = 0;
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initial begin
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$dumpfile("counter_tb.vcd");
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$dumpvars(0,counter_tb);
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# 0 reset = 1;
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# 4 reset = 0;
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# 36 reset = 1;
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# 4 reset = 0;
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# 6 $finish;
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end
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/* Make enable with period of 8 and 6,7 low */
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reg en = 1;
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always begin
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en = 1;
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#6;
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en = 0;
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#2;
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end
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/* Make a regular pulsing clock. */
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reg clk = 0;
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always #1 clk = !clk;
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/* UUT */
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wire [2:0] count;
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counter c1 (clk, reset, en, count);
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endmodule
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