mirror of https://github.com/YosysHQ/yosys.git
211 lines
6.0 KiB
C++
211 lines
6.0 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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void invert_gp_dff(Cell *cell, bool invert_input)
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{
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string cell_type = cell->type.str();
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bool cell_type_latch = cell_type.find("LATCH") != string::npos;
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bool cell_type_i = cell_type.find('I') != string::npos;
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bool cell_type_r = cell_type.find('R') != string::npos;
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bool cell_type_s = cell_type.find('S') != string::npos;
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if (!invert_input)
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{
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Const initval = cell->getParam(ID::INIT);
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if (GetSize(initval) >= 1) {
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if (initval.bits[0] == State::S0)
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initval.bits[0] = State::S1;
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else if (initval.bits[0] == State::S1)
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initval.bits[0] = State::S0;
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cell->setParam(ID::INIT, initval);
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}
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if (cell_type_r && cell_type_s)
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{
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Const srmode = cell->getParam(ID(SRMODE));
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if (GetSize(srmode) >= 1) {
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if (srmode.bits[0] == State::S0)
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srmode.bits[0] = State::S1;
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else if (srmode.bits[0] == State::S1)
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srmode.bits[0] = State::S0;
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cell->setParam(ID(SRMODE), srmode);
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}
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}
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else
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{
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if (cell_type_r) {
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cell->setPort(ID(nSET), cell->getPort(ID(nRST)));
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cell->unsetPort(ID(nRST));
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cell_type_r = false;
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cell_type_s = true;
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} else
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if (cell_type_s) {
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cell->setPort(ID(nRST), cell->getPort(ID(nSET)));
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cell->unsetPort(ID(nSET));
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cell_type_r = true;
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cell_type_s = false;
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}
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}
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}
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if (cell_type_i) {
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cell->setPort(ID::Q, cell->getPort(ID(nQ)));
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cell->unsetPort(ID(nQ));
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cell_type_i = false;
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} else {
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cell->setPort(ID(nQ), cell->getPort(ID::Q));
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cell->unsetPort(ID::Q);
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cell_type_i = true;
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}
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if(cell_type_latch)
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cell->type = stringf("\\GP_DLATCH%s%s%s", cell_type_s ? "S" : "", cell_type_r ? "R" : "", cell_type_i ? "I" : "");
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else
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cell->type = stringf("\\GP_DFF%s%s%s", cell_type_s ? "S" : "", cell_type_r ? "R" : "", cell_type_i ? "I" : "");
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log("Merged %s inverter into cell %s.%s: %s -> %s\n", invert_input ? "input" : "output",
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log_id(cell->module), log_id(cell), cell_type.c_str()+1, log_id(cell->type));
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}
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struct Greenpak4DffInvPass : public Pass {
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Greenpak4DffInvPass() : Pass("greenpak4_dffinv", "merge greenpak4 inverters and DFF/latches") { }
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void help() override
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{
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log("\n");
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log(" greenpak4_dffinv [options] [selection]\n");
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log("\n");
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log("Merge GP_INV cells with GP_DFF* and GP_DLATCH* cells.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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log_header(design, "Executing GREENPAK4_DFFINV pass (merge input/output inverters into FF/latch cells).\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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// if (args[argidx] == "-singleton") {
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// singleton_mode = true;
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// continue;
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// }
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break;
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}
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extra_args(args, argidx, design);
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pool<IdString> gp_dff_types;
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gp_dff_types.insert(ID(GP_DFF));
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gp_dff_types.insert(ID(GP_DFFI));
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gp_dff_types.insert(ID(GP_DFFR));
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gp_dff_types.insert(ID(GP_DFFRI));
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gp_dff_types.insert(ID(GP_DFFS));
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gp_dff_types.insert(ID(GP_DFFSI));
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gp_dff_types.insert(ID(GP_DFFSR));
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gp_dff_types.insert(ID(GP_DFFSRI));
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gp_dff_types.insert(ID(GP_DLATCH));
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gp_dff_types.insert(ID(GP_DLATCHI));
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gp_dff_types.insert(ID(GP_DLATCHR));
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gp_dff_types.insert(ID(GP_DLATCHRI));
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gp_dff_types.insert(ID(GP_DLATCHS));
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gp_dff_types.insert(ID(GP_DLATCHSI));
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gp_dff_types.insert(ID(GP_DLATCHSR));
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gp_dff_types.insert(ID(GP_DLATCHSRI));
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for (auto module : design->selected_modules())
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{
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SigMap sigmap(module);
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dict<SigBit, int> sig_use_cnt;
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dict<SigBit, SigBit> inv_in2out, inv_out2in;
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dict<SigBit, Cell*> inv_in2cell;
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pool<Cell*> dff_cells;
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for (auto wire : module->wires())
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{
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if (!wire->port_output)
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continue;
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for (auto bit : sigmap(wire))
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sig_use_cnt[bit]++;
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}
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for (auto cell : module->cells())
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for (auto &conn : cell->connections())
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if (cell->input(conn.first) || !cell->known())
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for (auto bit : sigmap(conn.second))
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sig_use_cnt[bit]++;
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for (auto cell : module->selected_cells())
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{
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if (gp_dff_types.count(cell->type)) {
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dff_cells.insert(cell);
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continue;
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}
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if (cell->type == ID(GP_INV)) {
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SigBit in_bit = sigmap(cell->getPort(ID(IN)));
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SigBit out_bit = sigmap(cell->getPort(ID(OUT)));
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inv_in2out[in_bit] = out_bit;
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inv_out2in[out_bit] = in_bit;
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inv_in2cell[in_bit] = cell;
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continue;
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}
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}
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for (auto cell : dff_cells)
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{
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SigBit d_bit = sigmap(cell->getPort(ID::D));
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SigBit q_bit = sigmap(cell->hasPort(ID::Q) ? cell->getPort(ID::Q) : cell->getPort(ID(nQ)));
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while (inv_out2in.count(d_bit))
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{
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sig_use_cnt[d_bit]--;
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invert_gp_dff(cell, true);
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d_bit = inv_out2in.at(d_bit);
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cell->setPort(ID::D, d_bit);
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sig_use_cnt[d_bit]++;
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}
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while (inv_in2out.count(q_bit) && sig_use_cnt[q_bit] == 1)
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{
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SigBit new_q_bit = inv_in2out.at(q_bit);
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module->remove(inv_in2cell.at(q_bit));
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sig_use_cnt.erase(q_bit);
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inv_in2out.erase(q_bit);
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inv_out2in.erase(new_q_bit);
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inv_in2cell.erase(q_bit);
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invert_gp_dff(cell, false);
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if (cell->hasPort(ID::Q))
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cell->setPort(ID::Q, new_q_bit);
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else
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cell->setPort(ID(nQ), new_q_bit);
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}
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}
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}
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}
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} Greenpak4DffInvPass;
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PRIVATE_NAMESPACE_END
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