yosys/passes
Martin Povišer 8b1f5fba62 passes: show: Simplify wire bit range logic
Signed-off-by: Martin Povišer <povik@cutebit.org>
2023-01-13 19:57:24 +01:00
..
cmds passes: show: Simplify wire bit range logic 2023-01-13 19:57:24 +01:00
equiv Add "check -assert" to equiv_opt 2022-10-07 16:04:51 +02:00
fsm mention prerequisites in fsm_detect and fsm help 2022-11-21 16:07:23 +01:00
hierarchy Small bugfix in uniquify pass 2022-12-21 10:41:48 +01:00
memory Fitting help messages to 80 character width 2022-08-24 10:40:57 +12:00
opt opt_expr: Optimizations for `$bweqx` and `$bwmux` 2022-11-30 18:50:53 +01:00
pmgen Fitting help messages to 80 character width 2022-08-24 10:40:57 +12:00
proc proc_rom: Add special handling of const-0 address bits. 2022-05-18 17:32:30 +02:00
sat Merge branch 'master' into claire/eqystuff 2023-01-11 16:33:08 +01:00
techmap Merge branch 'xprop' of github.com:jix/yosys into claire/eqystuff 2022-12-01 11:31:39 +01:00
tests Add $bmux and $demux cells. 2022-01-28 23:34:41 +01:00