mirror of https://github.com/YosysHQ/yosys.git
113 lines
2.8 KiB
TeX
113 lines
2.8 KiB
TeX
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\section{Yosys by example -- Advanced Synthesis}
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\begin{frame}
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\sectionpage
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\end{frame}
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\begin{frame}{Overview}
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This section contains 4 subsections:
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\begin{itemize}
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\item Using selections
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\item Advanced uses of techmap
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\item Coarse-grain synthesis
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\item Automatic design changes
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\end{itemize}
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\end{frame}
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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\subsection{Automatic design changes}
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\begin{frame}
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\subsectionpage
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\subsectionpagesuffix
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\end{frame}
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\subsubsection{Changing the design from Yosys}
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\begin{frame}{\subsubsecname}
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Yosys commands can be used to change the design in memory. Examples of this are:
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\begin{itemize}
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\item {\bf Changes in design hierarchy} \\
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Commands such as {\tt flatten} and {\tt submod} can be used to change the design hierarchy, i.e.
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flatten the hierarchy or moving parts of a module to a submodule. This has applications in synthesis
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scripts as well as in reverse engineering and analysis.
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\item {\bf Behavioral changes} \\
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Commands such as {\tt techmap} can be used to make behavioral changes to the design, for example
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changing asynchronous resets to synchronous resets. This has applications in design space exploration
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(evaluation of various architectures for one circuit).
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\end{itemize}
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\end{frame}
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\subsubsection{Example: Async reset to sync reset}
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\begin{frame}[t, fragile]{\subsubsecname}
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The following techmap map file replaces all positive-edge async reset flip-flops with
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positive-edge sync reset flip-flops. The code is taken from the example Yosys script
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for ASIC synthesis of the Amber ARMv2 CPU.
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\begin{columns}
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\column[t]{6cm}
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\vbox to 0cm{
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\begin{lstlisting}[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=Verilog]
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(* techmap_celltype = "$adff" *)
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module adff2dff (CLK, ARST, D, Q);
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parameter WIDTH = 1;
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parameter CLK_POLARITY = 1;
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parameter ARST_POLARITY = 1;
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parameter ARST_VALUE = 0;
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input CLK, ARST;
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input [WIDTH-1:0] D;
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output reg [WIDTH-1:0] Q;
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wire [1023:0] _TECHMAP_DO_ = "proc";
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wire _TECHMAP_FAIL_ = !CLK_POLARITY || !ARST_POLARITY;
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\end{lstlisting}
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\vss}
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\column[t]{4cm}
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\begin{lstlisting}[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=Verilog]
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// ..continued..
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always @(posedge CLK)
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if (ARST)
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Q <= ARST_VALUE;
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else
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<= D;
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endmodule
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\end{lstlisting}
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\end{columns}
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\end{frame}
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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\subsection{Summary}
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\begin{frame}{\subsecname}
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\begin{itemize}
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\item A lot can be achieved in Yosys just with the standard set of commands.
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\item The commands {\tt techmap} and {\tt extract} can be used to prototype many complex synthesis tasks.
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\end{itemize}
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\bigskip
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\bigskip
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\begin{center}
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Questions?
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\end{center}
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\bigskip
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\bigskip
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\begin{center}
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\url{https://yosyshq.net/yosys/}
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\end{center}
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\end{frame}
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