yosys/docs/resources/PRESENTATION_ExAdv/macc_simple_xmap.v

7 lines
116 B
Verilog

module macc_16_16_32(a, b, c, y);
input [15:0] a, b;
input [31:0] c;
output [31:0] y;
assign y = a*b + c;
endmodule