mirror of https://github.com/YosysHQ/yosys.git
21 lines
511 B
Verilog
21 lines
511 B
Verilog
module \$add (A, B, Y);
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter A_WIDTH = 1;
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parameter B_WIDTH = 1;
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parameter Y_WIDTH = 1;
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input [A_WIDTH-1:0] A;
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input [B_WIDTH-1:0] B;
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output [Y_WIDTH-1:0] Y;
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parameter _TECHMAP_BITS_CONNMAP_ = 0;
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parameter _TECHMAP_CONNMAP_A_ = 0;
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parameter _TECHMAP_CONNMAP_B_ = 0;
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wire _TECHMAP_FAIL_ = A_WIDTH != B_WIDTH || B_WIDTH < Y_WIDTH ||
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_TECHMAP_CONNMAP_A_ != _TECHMAP_CONNMAP_B_;
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assign Y = A << 1;
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endmodule
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