mirror of https://github.com/YosysHQ/yosys.git
132 lines
3.2 KiB
Verilog
132 lines
3.2 KiB
Verilog
// Intel megafunction declarations, to avoid Yosys complaining.
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`default_nettype none
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(* blackbox *)
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module altera_std_synchronizer(clk, din, dout, reset_n);
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parameter depth = 2;
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input clk;
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input reset_n;
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input din;
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output dout;
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endmodule
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(* blackbox *)
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module altiobuf_in(datain, dataout);
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parameter enable_bus_hold = "FALSE";
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parameter use_differential_mode = "FALSE";
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parameter number_of_channels = 1;
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input [number_of_channels-1:0] datain;
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output [number_of_channels-1:0] dataout;
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endmodule
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(* blackbox *)
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module altiobuf_out(datain, dataout);
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parameter enable_bus_hold = "FALSE";
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parameter use_differential_mode = "FALSE";
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parameter use_oe = "FALSE";
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parameter number_of_channels = 1;
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input [number_of_channels-1:0] datain;
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output [number_of_channels-1:0] dataout;
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endmodule
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(* blackbox *)
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module altiobuf_bidir(dataio, oe, datain, dataout);
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parameter number_of_channels = 1;
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parameter enable_bus_hold = "OFF";
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inout [number_of_channels-1:0] dataio;
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input [number_of_channels-1:0] datain;
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output [number_of_channels-1:0] dataout;
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input [number_of_channels-1:0] oe;
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endmodule
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(* blackbox *)
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module altsyncram(clock0, clock1, address_a, data_a, rden_a, wren_a, byteena_a, q_a, addressstall_a, address_b, data_b, rden_b, wren_b, byteena_b, q_b, addressstall_b, clocken0, clocken1, clocken2, clocken3, aclr0, aclr1, eccstatus);
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parameter lpm_type = "altsyncram";
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parameter operation_mode = "dual_port";
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parameter ram_block_type = "auto";
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parameter intended_device_family = "auto";
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parameter power_up_uninitialized = "false";
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parameter read_during_write_mode_mixed_ports = "dontcare";
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parameter byte_size = 8;
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parameter widthad_a = 1;
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parameter width_a = 1;
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parameter width_byteena_a = 1;
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parameter numwords_a = 1;
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parameter clock_enable_input_a = "clocken0";
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parameter widthad_b = 1;
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parameter width_b = 1;
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parameter numwords_b = 1;
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parameter address_aclr_b = "aclr0";
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parameter address_reg_b = "";
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parameter outdata_aclr_b = "aclr0";
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parameter outdata_reg_b = "";
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parameter clock_enable_input_b = "clocken0";
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parameter clock_enable_output_b = "clocken0";
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input clock0, clock1;
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input [widthad_a-1:0] address_a;
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input [width_a-1:0] data_a;
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input rden_a;
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input wren_a;
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input [(width_a/8)-1:0] byteena_a;
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input addressstall_a;
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output [width_a-1:0] q_a;
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input wren_b;
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input rden_b;
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input [widthad_b-1:0] address_b;
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input [width_b-1:0] data_b;
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input [(width_b/8)-1:0] byteena_b;
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input addressstall_b;
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output [width_b-1:0] q_b;
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input clocken0;
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input clocken1;
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input clocken2;
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input clocken3;
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input aclr0;
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input aclr1;
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output eccstatus;
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endmodule
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(* blackbox *)
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module cyclonev_mlab_cell(portaaddr, portadatain, portbaddr, portbdataout, ena0, clk0, clk1);
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parameter logical_ram_name = "";
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parameter logical_ram_depth = 32;
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parameter logical_ram_width = 20;
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parameter mixed_port_feed_through_mode = "new";
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parameter first_bit_number = 0;
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parameter first_address = 0;
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parameter last_address = 31;
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parameter address_width = 5;
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parameter data_width = 1;
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parameter byte_enable_mask_width = 1;
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parameter port_b_data_out_clock = "NONE";
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parameter [639:0] mem_init0 = 640'b0;
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input [address_width-1:0] portaaddr, portbaddr;
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input [data_width-1:0] portadatain;
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output [data_width-1:0] portbdataout;
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input ena0, clk0, clk1;
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endmodule
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