mirror of https://github.com/YosysHQ/yosys.git
125 lines
5.5 KiB
Verilog
125 lines
5.5 KiB
Verilog
`default_nettype none
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// D flip-flops
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module \$_DFF_P_ (input D, C, output Q);
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parameter _TECHMAP_WIREINIT_Q_ = 1'b0;
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if (_TECHMAP_WIREINIT_Q_ !== 1'b1) begin
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wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
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MISTRAL_FF _TECHMAP_REPLACE_(.DATAIN(D), .CLK(C), .ACLR(1'b1), .ENA(1'b1), .SCLR(1'b0), .SLOAD(1'b0), .SDATA(1'b0), .Q(Q));
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end else $error("Cannot implement a flip-flop that initialises to one");
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endmodule
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module \$_DFF_N_ (input D, C, output Q);
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parameter _TECHMAP_WIREINIT_Q_ = 1'b0;
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if (_TECHMAP_WIREINIT_Q_ !== 1'b1) begin
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wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
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MISTRAL_FF _TECHMAP_REPLACE_(.DATAIN(D), .CLK(~C), .ACLR(1'b1), .ENA(1'b1), .SCLR(1'b0), .SLOAD(1'b0), .SDATA(1'b0), .Q(Q));
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end else $error("Cannot implement a flip-flop that initialises to one");
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endmodule
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// D flip-flops with reset
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module \$_DFF_PP0_ (input D, C, R, output Q);
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parameter _TECHMAP_WIREINIT_Q_ = 1'b0;
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if (_TECHMAP_WIREINIT_Q_ !== 1'b1) begin
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wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
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MISTRAL_FF _TECHMAP_REPLACE_(.DATAIN(D), .CLK(C), .ACLR(~R), .ENA(1'b1), .SCLR(1'b0), .SLOAD(1'b0), .SDATA(1'b0), .Q(Q));
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end else $error("Cannot implement a flip-flop with reset that initialises to one");
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endmodule
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module \$_DFF_PN0_ (input D, C, R, output Q);
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parameter _TECHMAP_WIREINIT_Q_ = 1'b0;
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if (_TECHMAP_WIREINIT_Q_ !== 1'b1) begin
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wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
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MISTRAL_FF _TECHMAP_REPLACE_(.DATAIN(D), .CLK(C), .ACLR(R), .ENA(1'b1), .SCLR(1'b0), .SLOAD(1'b0), .SDATA(1'b0), .Q(Q));
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end else $error("Cannot implement a flip-flop with reset that initialises to one");
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endmodule
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module \$_DFF_NP0_ (input D, C, R, output Q);
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parameter _TECHMAP_WIREINIT_Q_ = 1'b0;
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if (_TECHMAP_WIREINIT_Q_ !== 1'b1) begin
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wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
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MISTRAL_FF _TECHMAP_REPLACE_(.DATAIN(D), .CLK(~C), .ACLR(~R), .ENA(1'b1), .SCLR(1'b0), .SLOAD(1'b0), .SDATA(1'b0), .Q(Q));
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end else $error("Cannot implement a flip-flop with reset that initialises to one");
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endmodule
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module \$_DFF_NN0_ (input D, C, R, output Q);
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parameter _TECHMAP_WIREINIT_Q_ = 1'b0;
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if (_TECHMAP_WIREINIT_Q_ !== 1'b1) begin
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wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
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MISTRAL_FF _TECHMAP_REPLACE_(.DATAIN(D), .CLK(~C), .ACLR(R), .ENA(1'b1), .SCLR(1'b0), .SLOAD(1'b0), .SDATA(1'b0), .Q(Q));
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end else $error("Cannot implement a flip-flop with reset that initialises to one");
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endmodule
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// D flip-flops with set
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module \$_DFF_PP1_ (input D, C, R, output Q);
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parameter _TECHMAP_WIREINIT_Q_ = 1'b1;
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if (_TECHMAP_WIREINIT_Q_ !== 1'b0) begin
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wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
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wire Q_tmp;
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MISTRAL_FF _TECHMAP_REPLACE_(.DATAIN(~D), .CLK(C), .ACLR(~R), .ENA(1'b1), .SCLR(1'b0), .SLOAD(1'b0), .SDATA(1'b0), .Q(Q_tmp));
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assign Q = ~Q_tmp;
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end else $error("Cannot implement a flip-flop with set that initialises to zero");
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endmodule
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module \$_DFF_PN1_ (input D, C, R, output Q);
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parameter _TECHMAP_WIREINIT_Q_ = 1'b1;
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if (_TECHMAP_WIREINIT_Q_ !== 1'b0) begin
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wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
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wire Q_tmp;
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MISTRAL_FF _TECHMAP_REPLACE_(.DATAIN(~D), .CLK(C), .ACLR(R), .ENA(1'b1), .SCLR(1'b0), .SLOAD(1'b0), .SDATA(1'b0), .Q(Q_tmp));
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end else $error("Cannot implement a flip-flop with set that initialises to zero");
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endmodule
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module \$_DFF_NP1_ (input D, C, R, output Q);
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parameter _TECHMAP_WIREINIT_Q_ = 1'b1;
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if (_TECHMAP_WIREINIT_Q_ !== 1'b0) begin
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wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
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wire Q_tmp;
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MISTRAL_FF _TECHMAP_REPLACE_(.DATAIN(~D), .CLK(~C), .ACLR(~R), .ENA(1'b1), .SCLR(1'b0), .SLOAD(1'b0), .SDATA(1'b0), .Q(Q_tmp));
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assign Q = ~Q_tmp;
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end else $error("Cannot implement a flip-flop with set that initialises to zero");
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endmodule
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module \$_DFF_NN1_ (input D, C, R, output Q);
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parameter _TECHMAP_WIREINIT_Q_ = 1'b1;
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if (_TECHMAP_WIREINIT_Q_ !== 1'b0) begin
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wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
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wire Q_tmp;
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MISTRAL_FF _TECHMAP_REPLACE_(.DATAIN(~D), .CLK(~C), .ACLR(R), .ENA(1'b1), .SCLR(1'b0), .SLOAD(1'b0), .SDATA(1'b0), .Q(Q_tmp));
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assign Q = ~Q_tmp;
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end else $error("Cannot implement a flip-flop with set that initialises to zero");
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endmodule
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// D flip-flops with clock enable
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module \$_DFFE_PP_ (input D, C, E, output Q);
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parameter _TECHMAP_WIREINIT_Q_ = 1'b0;
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if (_TECHMAP_WIREINIT_Q_ !== 1'b1) begin
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wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
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MISTRAL_FF _TECHMAP_REPLACE_(.DATAIN(D), .CLK(C), .ACLR(1'b1), .ENA(E), .SCLR(1'b0), .SLOAD(1'b0), .SDATA(1'b0), .Q(Q));
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end else $error("Cannot implement a flip-flop with enable that initialises to one");
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endmodule
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module \$_DFFE_PN_ (input D, C, E, output Q);
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parameter _TECHMAP_WIREINIT_Q_ = 1'b0;
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if (_TECHMAP_WIREINIT_Q_ !== 1'b1) begin
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wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
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MISTRAL_FF _TECHMAP_REPLACE_(.DATAIN(D), .CLK(C), .ACLR(1'b1), .ENA(~E), .SCLR(1'b0), .SLOAD(1'b0), .SDATA(1'b0), .Q(Q));
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end else $error("Cannot implement a flip-flop with enable that initialises to one");
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endmodule
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module \$_DFFE_NP_ (input D, C, E, output Q);
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parameter _TECHMAP_WIREINIT_Q_ = 1'b0;
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if (_TECHMAP_WIREINIT_Q_ !== 1'b1) begin
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wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
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MISTRAL_FF _TECHMAP_REPLACE_(.DATAIN(D), .CLK(~C), .ACLR(1'b1), .ENA(E), .SCLR(1'b0), .SLOAD(1'b0), .SDATA(1'b0), .Q(Q));
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end else $error("Cannot implement a flip-flop with enable that initialises to one");
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endmodule
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module \$_DFFE_NN_ (input D, C, E, output Q);
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parameter _TECHMAP_WIREINIT_Q_ = 1'b0;
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if (_TECHMAP_WIREINIT_Q_ !== 1'b1) begin
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wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
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MISTRAL_FF _TECHMAP_REPLACE_(.DATAIN(D), .CLK(~C), .ACLR(1'b1), .ENA(~E), .SCLR(1'b0), .SLOAD(1'b0), .SDATA(1'b0), .Q(Q));
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end else $error("Cannot implement a flip-flop with enable that initialises to one");
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endmodule
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