mirror of https://github.com/YosysHQ/yosys.git
238 lines
7.1 KiB
C++
238 lines
7.1 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/register.h"
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#include "kernel/log.h"
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#include <stdlib.h>
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#include <assert.h>
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#include <stdio.h>
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#include <string.h>
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#include "passes/techmap/stdcells.inc"
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static void apply_prefix(std::string prefix, std::string &id)
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{
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if (id[0] == '\\')
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id = prefix + "." + id.substr(1);
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else
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id = prefix + "." + id;
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}
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static void apply_prefix(std::string prefix, RTLIL::SigSpec &sig, RTLIL::Module *module)
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{
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for (size_t i = 0; i < sig.chunks.size(); i++) {
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if (sig.chunks[i].wire == NULL)
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continue;
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std::string wire_name = sig.chunks[i].wire->name;
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apply_prefix(prefix, wire_name);
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assert(module->wires.count(wire_name) > 0);
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sig.chunks[i].wire = module->wires[wire_name];
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}
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}
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std::map<std::pair<RTLIL::IdString, std::map<RTLIL::IdString, RTLIL::Const>>, RTLIL::Module*> techmap_cache;
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static bool techmap_module(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Design *map)
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{
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if (!design->selected(module))
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return false;
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bool did_something = false;
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std::vector<std::string> cell_names;
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for (auto &cell_it : module->cells)
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cell_names.push_back(cell_it.first);
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for (auto &cell_name : cell_names)
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{
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if (module->cells.count(cell_name) == 0)
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continue;
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RTLIL::Cell *cell = module->cells[cell_name];
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if (!design->selected(module, cell))
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continue;
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if (map->modules.count(cell->type) == 0)
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continue;
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RTLIL::Module *tpl = map->modules[cell->type];
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std::pair<RTLIL::IdString, std::map<RTLIL::IdString, RTLIL::Const>> key(cell->type, cell->parameters);
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if (techmap_cache.count(key) > 0) {
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tpl = techmap_cache[key];
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} else {
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std::string derived_name = cell->type;
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if (cell->parameters.size() != 0) {
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derived_name = tpl->derive(map, cell->parameters);
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tpl = map->modules[derived_name];
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log_header("Continuing TECHMAP pass.\n");
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}
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for (auto &cit : tpl->cells)
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if (cit.second->type == "\\TECHMAP_FAILED") {
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log("Not using module `%s' from techmap as it contains a TECHMAP_FAILED marker cell.\n", derived_name.c_str());
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tpl = NULL;
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break;
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}
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techmap_cache[key] = tpl;
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}
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if (tpl == NULL)
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goto next_cell;
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log("Mapping `%s.%s' using `%s'.\n", module->name.c_str(), cell_name.c_str(), tpl->name.c_str());
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if (tpl->memories.size() != 0)
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log_error("Technology map yielded memories -> this is not supported.");
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if (tpl->processes.size() != 0)
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log_error("Technology map yielded processes -> this is not supported.");
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for (auto &it : tpl->wires) {
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RTLIL::Wire *w = new RTLIL::Wire(*it.second);
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apply_prefix(cell_name, w->name);
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w->port_input = false;
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w->port_output = false;
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w->port_id = 0;
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module->wires[w->name] = w;
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design->select(module, w);
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}
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for (auto &it : tpl->cells) {
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RTLIL::Cell *c = new RTLIL::Cell(*it.second);
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if (c->type.substr(0, 2) == "\\$")
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c->type = c->type.substr(1);
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apply_prefix(cell_name, c->name);
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for (auto &it2 : c->connections)
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apply_prefix(cell_name, it2.second, module);
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module->cells[c->name] = c;
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design->select(module, c);
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}
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for (auto &it : tpl->connections) {
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RTLIL::SigSig c = it;
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apply_prefix(cell_name, c.first, module);
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apply_prefix(cell_name, c.second, module);
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module->connections.push_back(c);
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}
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for (auto &it : cell->connections) {
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assert(tpl->wires.count(it.first));
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assert(tpl->wires[it.first]->port_id > 0);
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RTLIL::Wire *w = tpl->wires[it.first];
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RTLIL::SigSig c;
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if (w->port_output) {
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c.first = it.second;
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c.second = RTLIL::SigSpec(w);
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apply_prefix(cell_name, c.second, module);
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} else {
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c.first = RTLIL::SigSpec(w);
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c.second = it.second;
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apply_prefix(cell_name, c.first, module);
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}
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if (c.second.width > c.first.width)
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c.second.remove(c.first.width, c.second.width - c.first.width);
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if (c.second.width < c.first.width)
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c.second.append(RTLIL::SigSpec(RTLIL::State::S0, c.first.width - c.second.width));
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assert(c.first.width == c.second.width);
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module->connections.push_back(c);
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}
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delete cell;
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module->cells.erase(cell_name);
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did_something = true;
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next_cell:;
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}
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return did_something;
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}
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struct TechmapPass : public Pass {
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TechmapPass() : Pass("techmap", "simple technology mapper") { }
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virtual void help()
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" techmap [-map filename] [selection]\n");
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log("\n");
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log("This pass implements a very simple technology mapper than replaces cells in\n");
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log("the design with implementations given in form of a verilog or ilang source\n");
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log("file.\n");
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log("\n");
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log(" -map filename\n");
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log(" the library of cell implementations to be used.\n");
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log(" without this parameter a builtin library is used that\n");
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log(" transform the internal RTL cells to the internal gate\n");
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log(" library.\n");
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log("\n");
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log("See 'help extract' for a pass that does the opposite thing.\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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log_header("Executing TECHMAP pass (map to technology primitives).\n");
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log_push();
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std::string filename;
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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if (args[argidx] == "-map" && argidx+1 < args.size()) {
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filename = args[++argidx];
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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FILE *f = filename.empty() ? fmemopen(stdcells_code, strlen(stdcells_code), "rt") : fopen(filename.c_str(), "rt");
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if (f == NULL)
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log_cmd_error("Can't open map file `%s'\n", filename.c_str());
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RTLIL::Design *map = new RTLIL::Design;
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Frontend::frontend_call(map, f, filename.empty() ? "<stdcells.v>" : filename,
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(filename.size() > 3 && filename.substr(filename.size()-3) == ".il") ? "ilang" : "verilog");
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fclose(f);
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std::map<RTLIL::IdString, RTLIL::Module*> modules_new;
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for (auto &it : map->modules) {
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if (it.first.substr(0, 2) == "\\$")
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it.second->name = it.first.substr(1);
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modules_new[it.second->name] = it.second;
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}
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map->modules.swap(modules_new);
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bool did_something = true;
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while (did_something) {
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did_something = false;
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for (auto &mod_it : design->modules)
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if (techmap_module(design, mod_it.second, map))
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did_something = true;
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}
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log("No more expansions possible.\n");
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techmap_cache.clear();
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delete map;
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log_pop();
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}
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} TechmapPass;
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