mirror of https://github.com/YosysHQ/yosys.git
97 lines
1.8 KiB
Verilog
97 lines
1.8 KiB
Verilog
`timescale 1ns / 1ps
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module testbench;
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parameter SIZEIN = 16, SIZEOUT = 40;
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reg clk, ce, rst;
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reg signed [SIZEIN-1:0] a, b;
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output signed [SIZEOUT-1:0] REF_accum_out, accum_out;
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output REF_overflow, overflow;
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integer errcount = 0;
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reg ERROR_FLAG = 0;
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task clkcycle;
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begin
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#5;
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clk = ~clk;
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#10;
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clk = ~clk;
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#2;
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ERROR_FLAG = 0;
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if (REF_accum_out !== accum_out) begin
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$display("ERROR at %1t: REF_accum_out=%b UUT_accum_out=%b DIFF=%b", $time, REF_accum_out, accum_out, REF_accum_out ^ accum_out);
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errcount = errcount + 1;
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ERROR_FLAG = 1;
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end
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if (REF_overflow !== overflow) begin
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$display("ERROR at %1t: REF_overflow=%b UUT_overflow=%b DIFF=%b", $time, REF_overflow, overflow, REF_overflow ^ overflow);
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errcount = errcount + 1;
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ERROR_FLAG = 1;
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end
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#3;
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end
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endtask
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initial begin
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//$dumpfile("test_macc.vcd");
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//$dumpvars(0, testbench);
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#2;
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clk = 1'b0;
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ce = 1'b0;
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a = 0;
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b = 0;
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rst = 1'b1;
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repeat (10) begin
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#10;
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clk = 1'b1;
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#10;
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clk = 1'b0;
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#10;
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clk = 1'b1;
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#10;
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clk = 1'b0;
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end
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rst = 1'b0;
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repeat (10000) begin
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clkcycle;
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ce = 1; //$urandom & $urandom;
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//rst = $urandom & $urandom & $urandom & $urandom & $urandom & $urandom;
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a = $urandom & ~(1 << (SIZEIN-1));
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b = $urandom & ~(1 << (SIZEIN-1));
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end
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if (errcount == 0) begin
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$display("All tests passed.");
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$finish;
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end else begin
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$display("Caught %1d errors.", errcount);
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$stop;
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end
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end
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macc2 ref (
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.clk(clk),
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.ce(ce),
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.rst(rst),
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.a(a),
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.b(b),
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.accum_out(REF_accum_out),
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.overflow(REF_overflow)
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);
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macc2_uut uut (
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.clk(clk),
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.ce(ce),
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.rst(rst),
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.a(a),
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.b(b),
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.accum_out(accum_out),
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.overflow(overflow)
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);
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endmodule
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