mirror of https://github.com/YosysHQ/yosys.git
51 lines
1.4 KiB
Plaintext
51 lines
1.4 KiB
Plaintext
read_verilog ../common/mul.v
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chparam -set X_WIDTH 8 -set Y_WIDTH 8 -set A_WIDTH 16
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hierarchy -top top
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proc
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design -save read
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equiv_opt -assert -map +/nexus/cells_sim.v synth_nexus
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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select -assert-count 1 t:MULT9X9
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select -assert-none t:IB t:OB t:VLO t:VHI t:MULT9X9 %% t:* %D
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design -reset
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read_verilog ../common/mul.v
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chparam -set X_WIDTH 16 -set Y_WIDTH 16 -set A_WIDTH 32
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hierarchy -top top
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proc
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# equivalence checking is too slow here
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synth_nexus
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cd top # Constrain all select calls below inside the top module
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select -assert-count 1 t:MULT18X18
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select -assert-none t:IB t:OB t:VLO t:VHI t:MULT18X18 %% t:* %D
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design -reset
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read_verilog ../common/mul.v
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chparam -set X_WIDTH 32 -set Y_WIDTH 16 -set A_WIDTH 48
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hierarchy -top top
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proc
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# equivalence checking is too slow here
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synth_nexus
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cd top # Constrain all select calls below inside the top module
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select -assert-count 1 t:MULT18X36
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select -assert-none t:IB t:OB t:VLO t:VHI t:MULT18X36 %% t:* %D
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design -reset
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read_verilog ../common/mul.v
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chparam -set X_WIDTH 32 -set Y_WIDTH 32 -set A_WIDTH 64
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hierarchy -top top
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proc
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# equivalence checking is too slow here
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synth_nexus
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cd top # Constrain all select calls below inside the top module
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select -assert-count 1 t:MULT36X36
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select -assert-none t:IB t:OB t:VLO t:VHI t:MULT36X36 %% t:* %D
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