mirror of https://github.com/YosysHQ/yosys.git
889297c62a
In an initial statement, blocking assignments are normally used and e.g. verilator throws a warning if non-blocking ones are used. Yosys cannot however properly resolve the interdependencies if blocking assignments are used in the initialization of SB_RAM_40_4K and thus this has been used. This patch will change to use non-blocking assignments only for yosys |
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| .. | ||
| tests | ||
| .gitignore | ||
| Makefile.inc | ||
| arith_map.v | ||
| brams.txt | ||
| brams_init.py | ||
| brams_map.v | ||
| cells_map.v | ||
| cells_sim.v | ||
| ice40_ffinit.cc | ||
| ice40_ffssr.cc | ||
| ice40_opt.cc | ||
| ice40_unlut.cc | ||
| latches_map.v | ||
| synth_ice40.cc | ||