mirror of https://github.com/YosysHQ/yosys.git
12 lines
316 B
Verilog
12 lines
316 B
Verilog
module test(in1, in2, out, vin1, vin2, vin3, vin4, vout1, vout2, en1, ven1, ven2);
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input in1, in2, en1, ven1;
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input [1:0] ven2;
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output out;
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input [1:0] vin1, vin2, vin3, vin4;
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output [1:0] vout1, vout2;
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assign out = en1 ? in1 : in2;
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assign vout1 = ven1 ? vin1 : vin2;
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assign vout2 = ven2 ? vin3 : vin4;
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endmodule
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