mirror of https://github.com/YosysHQ/yosys.git
78 lines
1.3 KiB
Verilog
78 lines
1.3 KiB
Verilog
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module test00(clk, setA, setB, y);
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input clk, setA, setB;
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output y;
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reg mem [1:0];
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always @(posedge clk) begin
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if (setA) mem[0] <= 0; // this is line 9
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if (setB) mem[0] <= 1; // this is line 10
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end
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assign y = mem[0];
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endmodule
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// ----------------------------------------------------------
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module test01(clk, wr_en, wr_addr, wr_value, rd_addr, rd_value);
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input clk, wr_en;
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input [3:0] wr_addr, rd_addr;
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input [7:0] wr_value;
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output reg [7:0] rd_value;
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reg [7:0] data [15:0];
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always @(posedge clk)
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if (wr_en)
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data[wr_addr] <= wr_value;
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always @(posedge clk)
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rd_value <= data[rd_addr];
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endmodule
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// ----------------------------------------------------------
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module test02(clk, setA, setB, addr, bit, y1, y2, y3, y4);
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input clk, setA, setB;
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input [1:0] addr;
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input [2:0] bit;
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output reg y1, y2;
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output y3, y4;
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reg [7:0] mem1 [3:0];
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(* mem2reg *)
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reg [7:0] mem2 [3:0];
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always @(posedge clk) begin
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if (setA) begin
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mem1[0] <= 10;
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mem1[1] <= 20;
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mem1[2] <= 30;
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mem2[0] <= 17;
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mem2[1] <= 27;
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mem2[2] <= 37;
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end
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if (setB) begin
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mem1[0] <= 1;
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mem1[1] <= 2;
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mem1[2] <= 3;
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mem2[0] <= 71;
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mem2[1] <= 72;
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mem2[2] <= 73;
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end
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y1 <= mem1[addr][bit];
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y2 <= mem2[addr][bit];
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end
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assign y3 = mem1[addr][bit];
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assign y4 = mem2[addr][bit];
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endmodule
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