mirror of https://github.com/YosysHQ/yosys.git
228 lines
6.9 KiB
C++
228 lines
6.9 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/register.h"
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#include "kernel/log.h"
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#include <stdlib.h>
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#include <assert.h>
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#include <sstream>
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static void normalize_sig(RTLIL::Module *module, RTLIL::SigSpec &sig)
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{
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for (auto &conn : module->connections)
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sig.replace(conn.first, conn.second);
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}
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static bool find_sig_before_dff(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLIL::SigSpec &clk, bool &clk_polarity, bool after = false)
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{
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normalize_sig(module, sig);
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sig.expand();
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for (size_t i = 0; i < sig.chunks().size(); i++)
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{
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RTLIL::SigChunk &chunk = sig.chunks_rw()[i];
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if (chunk.wire == NULL)
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continue;
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for (auto &cell_it : module->cells)
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{
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RTLIL::Cell *cell = cell_it.second;
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if (cell->type != "$dff")
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continue;
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if (clk != RTLIL::SigSpec(RTLIL::State::Sx)) {
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if (cell->connections["\\CLK"] != clk)
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continue;
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if (cell->parameters["\\CLK_POLARITY"].as_bool() != clk_polarity)
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continue;
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}
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RTLIL::SigSpec q_norm = cell->connections[after ? "\\D" : "\\Q"];
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normalize_sig(module, q_norm);
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RTLIL::SigSpec d = q_norm.extract(chunk, &cell->connections[after ? "\\Q" : "\\D"]);
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if (d.size() != 1)
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continue;
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assert(d.chunks().size() == 1);
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chunk = d.chunks()[0];
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clk = cell->connections["\\CLK"];
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clk_polarity = cell->parameters["\\CLK_POLARITY"].as_bool();
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goto replaced_this_bit;
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}
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return false;
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replaced_this_bit:;
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}
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sig.optimize();
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return true;
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}
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static void handle_wr_cell(RTLIL::Module *module, RTLIL::Cell *cell)
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{
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log("Checking cell `%s' in module `%s': ", cell->name.c_str(), module->name.c_str());
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RTLIL::SigSpec clk = RTLIL::SigSpec(RTLIL::State::Sx);
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bool clk_polarity = 0;
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RTLIL::SigSpec sig_addr = cell->connections["\\ADDR"];
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if (!find_sig_before_dff(module, sig_addr, clk, clk_polarity)) {
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log("no (compatible) $dff for address input found.\n");
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return;
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}
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RTLIL::SigSpec sig_data = cell->connections["\\DATA"];
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if (!find_sig_before_dff(module, sig_data, clk, clk_polarity)) {
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log("no (compatible) $dff for data input found.\n");
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return;
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}
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RTLIL::SigSpec sig_en = cell->connections["\\EN"];
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if (!find_sig_before_dff(module, sig_en, clk, clk_polarity)) {
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log("no (compatible) $dff for enable input found.\n");
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return;
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}
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if (clk != RTLIL::SigSpec(RTLIL::State::Sx)) {
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cell->connections["\\CLK"] = clk;
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cell->connections["\\ADDR"] = sig_addr;
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cell->connections["\\DATA"] = sig_data;
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cell->connections["\\EN"] = sig_en;
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cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(1);
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cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity);
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log("merged $dff to cell.\n");
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}
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log("no (compatible) $dff found.\n");
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}
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static void disconnect_dff(RTLIL::Module *module, RTLIL::SigSpec sig)
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{
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normalize_sig(module, sig);
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sig.sort_and_unify();
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std::stringstream sstr;
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sstr << "$memory_dff_disconnected$" << (RTLIL::autoidx++);
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RTLIL::Wire *wire = new RTLIL::Wire;
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wire->name = sstr.str();
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wire->width = sig.size();
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module->wires[wire->name] = wire;
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RTLIL::SigSpec newsig(wire);
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for (auto &cell_it : module->cells) {
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RTLIL::Cell *cell = cell_it.second;
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if (cell->type == "$dff")
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cell->connections["\\Q"].replace(sig, newsig);
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}
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}
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static void handle_rd_cell(RTLIL::Module *module, RTLIL::Cell *cell)
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{
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log("Checking cell `%s' in module `%s': ", cell->name.c_str(), module->name.c_str());
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bool clk_polarity = 0;
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RTLIL::SigSpec clk_data = RTLIL::SigSpec(RTLIL::State::Sx);
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RTLIL::SigSpec sig_data = cell->connections["\\DATA"];
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if (find_sig_before_dff(module, sig_data, clk_data, clk_polarity, true) &&
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clk_data != RTLIL::SigSpec(RTLIL::State::Sx))
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{
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disconnect_dff(module, sig_data);
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cell->connections["\\CLK"] = clk_data;
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cell->connections["\\DATA"] = sig_data;
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cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(1);
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cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity);
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cell->parameters["\\TRANSPARENT"] = RTLIL::Const(0);
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log("merged data $dff to cell.\n");
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return;
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}
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RTLIL::SigSpec clk_addr = RTLIL::SigSpec(RTLIL::State::Sx);
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RTLIL::SigSpec sig_addr = cell->connections["\\ADDR"];
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if (find_sig_before_dff(module, sig_addr, clk_addr, clk_polarity) &&
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clk_addr != RTLIL::SigSpec(RTLIL::State::Sx))
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{
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cell->connections["\\CLK"] = clk_addr;
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cell->connections["\\ADDR"] = sig_addr;
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cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(1);
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cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity);
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cell->parameters["\\TRANSPARENT"] = RTLIL::Const(1);
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log("merged address $dff to cell.\n");
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return;
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}
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log("no (compatible) $dff found.\n");
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}
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static void handle_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_wr_only)
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{
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for (auto &cell_it : module->cells) {
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if (!design->selected(module, cell_it.second))
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continue;
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if (cell_it.second->type == "$memwr" && !cell_it.second->parameters["\\CLK_ENABLE"].as_bool())
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handle_wr_cell(module, cell_it.second);
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if (!flag_wr_only && cell_it.second->type == "$memrd" && !cell_it.second->parameters["\\CLK_ENABLE"].as_bool())
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handle_rd_cell(module, cell_it.second);
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}
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}
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struct MemoryDffPass : public Pass {
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MemoryDffPass() : Pass("memory_dff", "merge input/output DFFs into memories") { }
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virtual void help()
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" memory_dff [options] [selection]\n");
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log("\n");
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log("This pass detects DFFs at memory ports and merges them into the memory port.\n");
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log("I.e. it consumes an asynchronous memory port and the flip-flops at its\n");
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log("interface and yields a synchronous memory port.\n");
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log("\n");
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log(" -wr_only\n");
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log(" do not merge registers on read ports\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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bool flag_wr_only = false;
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log_header("Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr).\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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if (args[argidx] == "-wr_only") {
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flag_wr_only = true;
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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for (auto &mod_it : design->modules)
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if (design->selected(mod_it.second))
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handle_module(design, mod_it.second, flag_wr_only);
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}
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} MemoryDffPass;
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