mirror of https://github.com/YosysHQ/yosys.git
121 lines
3.4 KiB
ReStructuredText
121 lines
3.4 KiB
ReStructuredText
Symbolic model checking
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-----------------------
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.. todo:: check text context
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.. note::
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While it is possible to perform model checking directly in Yosys, it
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is highly recommended to use SBY or EQY for formal hardware verification.
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Symbolic Model Checking (SMC) is used to formally prove that a circuit has (or
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has not) a given property.
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One application is Formal Equivalence Checking: Proving that two circuits are
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identical. For example this is a very useful feature when debugging custom
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passes in Yosys.
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Other applications include checking if a module conforms to interface standards.
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The `sat` command in Yosys can be used to perform Symbolic Model
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Checking.
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Checking techmap
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~~~~~~~~~~~~~~~~
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.. todo:: add/expand supporting text
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Let's take a look at an example included in the Yosys code base under
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|code_examples/synth_flow|_:
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.. |code_examples/synth_flow| replace:: :file:`docs/source/code_examples/synth_flow`
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.. _code_examples/synth_flow: https://github.com/YosysHQ/yosys/tree/main/docs/source/code_examples/synth_flow
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.. literalinclude:: /code_examples/synth_flow/techmap_01_map.v
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:language: verilog
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:caption: :file:`techmap_01_map.v`
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.. literalinclude:: /code_examples/synth_flow/techmap_01.v
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:language: verilog
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:caption: :file:`techmap_01.v`
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.. literalinclude:: /code_examples/synth_flow/techmap_01.ys
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:language: yoscrypt
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:caption: :file:`techmap_01.ys`
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To see if it is correct we can use the following code:
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.. todo:: replace inline code
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.. code:: yoscrypt
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# read test design
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read_verilog techmap_01.v
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hierarchy -top test
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# create two version of the design: test_orig and test_mapped
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copy test test_orig
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rename test test_mapped
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# apply the techmap only to test_mapped
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techmap -map techmap_01_map.v test_mapped
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# create a miter circuit to test equivalence
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miter -equiv -make_assert -make_outputs test_orig test_mapped miter
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flatten miter
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# run equivalence check
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sat -verify -prove-asserts -show-inputs -show-outputs miter
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Result:
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.. code::
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Solving problem with 945 variables and 2505 clauses..
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SAT proof finished - no model found: SUCCESS!
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AXI4 Stream Master
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~~~~~~~~~~~~~~~~~~
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The code used in this section is included in the Yosys code base under
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|code_examples/axis|_.
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.. |code_examples/axis| replace:: :file:`docs/source/code_examples/axis`
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.. _code_examples/axis: https://github.com/YosysHQ/yosys/tree/main/docs/source/code_examples/axis
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The following AXI4 Stream Master has a bug. But the bug is not exposed if the
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slave keeps ``tready`` asserted all the time. (Something a test bench might do.)
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Symbolic Model Checking can be used to expose the bug and find a sequence of
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values for ``tready`` that yield the incorrect behavior.
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.. todo:: add/expand supporting text
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.. literalinclude:: /code_examples/axis/axis_master.v
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:language: verilog
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:caption: :file:`axis_master.v`
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.. literalinclude:: /code_examples/axis/axis_test.v
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:language: verilog
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:caption: :file:`axis_test.v`
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.. literalinclude:: /code_examples/axis/axis_test.ys
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:language: yoscrypt
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:caption: :file:`test.ys`
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Result with unmodified :file:`axis_master.v`:
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.. todo:: replace inline code
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.. code::
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Solving problem with 159344 variables and 442126 clauses..
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SAT proof finished - model found: FAIL!
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Result with fixed :file:`axis_master.v`:
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.. code::
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Solving problem with 159144 variables and 441626 clauses..
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SAT proof finished - no model found: SUCCESS!
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