mirror of https://github.com/YosysHQ/yosys.git
31 lines
1.6 KiB
Verilog
31 lines
1.6 KiB
Verilog
module opt_rmdff_test (input C, input D, input E, output reg [16:0] Q);
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\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove0 (.CLK(C), .D(D), .EN(1'b0), .Q(Q[0]));
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initial Q[1] = 1'b1;
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\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove1 (.CLK(C), .D(D), .EN(1'b0), .Q(Q[1]));
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\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove2 (.CLK(C), .D(D), .EN(1'bx), .Q(Q[2]));
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\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) keep3 (.CLK(C), .D(D), .EN(1'b1), .Q(Q[3]));
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initial Q[3] = 1'b0;
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\$dffe #(.WIDTH(1), .CLK_POLARITY(0), .EN_POLARITY(1)) keep4 (.CLK(C), .D(D), .EN(1'b1), .Q(Q[4]));
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\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(0)) remove5 (.CLK(C), .D(D), .EN(1'b1), .Q(Q[5]));
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\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(0)) remove6 (.CLK(C), .D(D), .EN(1'bx), .Q(Q[6]));
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initial Q[6] = 1'b0;
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\$dffe #(.WIDTH(1), .CLK_POLARITY(0), .EN_POLARITY(0)) keep7 (.CLK(C), .D(D), .EN(E), .Q(Q[7]));
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\$_DFFE_PP_ remove8 (.C(C), .D(D), .E(1'b0), .Q(Q[8]));
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initial Q[8] = 1'b1;
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\$_DFFE_PP_ remove9 (.C(C), .D(D), .E(1'b0), .Q(Q[9]));
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\$_DFFE_PP_ remove10 (.C(C), .D(D), .E(1'bx), .Q(Q[10]));
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\$_DFFE_PP_ keep11 (.C(C), .D(D), .E(1'b1), .Q(Q[11]));
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initial Q[12] = 1'b0;
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\$_DFFE_PP_ keep12 (.C(C), .D(D), .E(1'b1), .Q(Q[12]));
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\$_DFFE_NN_ remove13 (.C(C), .D(D), .E(1'b1), .Q(Q[13]));
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initial Q[14] = 1'b1;
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\$_DFFE_NN_ remove14 (.C(C), .D(D), .E(1'b1), .Q(Q[14]));
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\$_DFFE_NN_ remove15 (.C(C), .D(D), .E(1'bx), .Q(Q[15]));
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\$_DFFE_NN_ keep16 (.C(C), .D(D), .E(1'b0), .Q(Q[16]));
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initial Q[17] = 1'b0;
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\$_DFFE_NN_ keep17 (.C(C), .D(D), .E(1'b0), .Q(Q[17]));
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endmodule
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