yosys/backends
Sahand Kashani 820e3d1dad Remove unnecessary pruning of double-quoting
In the past I was calling the ILANG_BACKEND::dump_const() to dump
values to an output stream. When these values were strings, the
function used to add quotes around them. The firrtl compiler, in turn,
escaped these quotes and the result was double-quoted strings which
were hard to read.

However I'm now calling design_entity->get_src_attribute() directly
and there is no additional quote being put around it, so we can
safely remove the unnecessary call to str.erase() here.
2020-04-08 23:20:56 +02:00
..
aiger xaiger: remove some unnecessary operations ... 2020-03-06 10:51:47 -08:00
blif RTLIL::S{0,1} -> State::S{0,1} 2019-08-07 11:12:38 -07:00
btor Use cell name for btor bad state props when it is a public name 2019-11-14 11:57:38 +01:00
edif edif: more resilience to mismatched port connection sizes. 2020-02-06 18:45:03 +01:00
firrtl Remove unnecessary pruning of double-quoting 2020-04-08 23:20:56 +02:00
ilang RTLIL::S{0,1} -> State::S{0,1} 2019-08-07 11:12:38 -07:00
intersynth substr() -> compare() 2019-08-07 12:20:08 -07:00
json json: Change compat mode to directly emit ints <= 32 bits 2020-02-09 01:01:18 -08:00
protobuf Add aiger and protobuf backends binary support 2019-09-28 09:51:48 +02:00
simplec Add $_NMUX_, add "abc -g cmos", add proper cmos cell costs 2019-08-06 04:47:55 +02:00
smt2 Merge pull request #1768 from boqwxp/smt2_cleanup 2020-03-16 13:49:10 +01:00
smv substr() -> compare() 2019-08-07 12:20:08 -07:00
spice Add "whitebox" attribute, add "read_verilog -wb" 2019-04-18 17:45:47 +02:00
table Add "whitebox" attribute, add "read_verilog -wb" 2019-04-18 17:45:47 +02:00
verilog specify: system timing checks to accept min:typ:max triple 2020-02-13 12:42:15 -08:00