mirror of https://github.com/YosysHQ/yosys.git
90 lines
1.5 KiB
Verilog
90 lines
1.5 KiB
Verilog
(* techmap_celltype = "$mul" *)
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module mul_wrap (A, B, Y);
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter A_WIDTH = 1;
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parameter B_WIDTH = 1;
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parameter Y_WIDTH = 1;
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input [A_WIDTH-1:0] A;
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input [B_WIDTH-1:0] B;
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output [Y_WIDTH-1:0] Y;
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wire [17:0] A_18 = A;
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wire [24:0] B_25 = B;
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wire [47:0] Y_48;
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assign Y = Y_48;
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wire [1023:0] _TECHMAP_DO_ = "proc; clean";
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reg _TECHMAP_FAIL_;
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initial begin
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_TECHMAP_FAIL_ <= 0;
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if (A_SIGNED || B_SIGNED)
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_TECHMAP_FAIL_ <= 1;
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if (A_WIDTH < 4 || B_WIDTH < 4)
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_TECHMAP_FAIL_ <= 1;
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if (A_WIDTH > 18 || B_WIDTH > 25)
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_TECHMAP_FAIL_ <= 1;
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if (A_WIDTH*B_WIDTH < 100)
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_TECHMAP_FAIL_ <= 1;
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end
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\$__mul_wrapper #(
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.A_SIGNED(A_SIGNED),
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.B_SIGNED(B_SIGNED),
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.A_WIDTH(A_WIDTH),
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.B_WIDTH(B_WIDTH),
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.Y_WIDTH(Y_WIDTH)
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) _TECHMAP_REPLACE_ (
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.A(A_18),
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.B(B_25),
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.Y(Y_48)
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);
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endmodule
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(* techmap_celltype = "$add" *)
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module add_wrap (A, B, Y);
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter A_WIDTH = 1;
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parameter B_WIDTH = 1;
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parameter Y_WIDTH = 1;
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input [A_WIDTH-1:0] A;
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input [B_WIDTH-1:0] B;
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output [Y_WIDTH-1:0] Y;
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wire [47:0] A_48 = A;
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wire [47:0] B_48 = B;
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wire [47:0] Y_48;
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assign Y = Y_48;
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wire [1023:0] _TECHMAP_DO_ = "proc; clean";
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reg _TECHMAP_FAIL_;
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initial begin
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_TECHMAP_FAIL_ <= 0;
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if (A_SIGNED || B_SIGNED)
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_TECHMAP_FAIL_ <= 1;
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if (A_WIDTH < 10 && B_WIDTH < 10)
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_TECHMAP_FAIL_ <= 1;
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end
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\$__add_wrapper #(
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.A_SIGNED(A_SIGNED),
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.B_SIGNED(B_SIGNED),
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.A_WIDTH(A_WIDTH),
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.B_WIDTH(B_WIDTH),
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.Y_WIDTH(Y_WIDTH)
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) _TECHMAP_REPLACE_ (
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.A(A_48),
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.B(B_48),
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.Y(Y_48)
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);
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endmodule
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