riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
yosys/backends/verilog
History
Clifford Wolf 7fa61cba1b Added "write_verilog -nodec -nostr" 2016-07-30 12:38:40 +02:00
..
Makefile.inc initial import 2013-01-05 11:13:26 +01:00
verilog_backend.cc Added "write_verilog -nodec -nostr" 2016-07-30 12:38:40 +02:00