Charlotte 7f7c61c9f0 fmt: remove lzero by lowering during Verilog parse ... See https://github.com/YosysHQ/yosys/pull/3721#issuecomment-1502037466 -- this reduces logic within the cell, and makes the rules that apply much more clear.		2023-08-11 04:46:52 +02:00
..
Makefile.inc	cxxrtl: rename cxxrtl.cc→cxxrtl_backend.cc.	2020-06-07 03:48:40 +00:00
cxxrtl.h	fmt: remove lzero by lowering during Verilog parse	2023-08-11 04:46:52 +02:00
cxxrtl_backend.cc	cxxrtl: restrict -print-output to cout, cerr	2023-08-11 04:46:52 +02:00
cxxrtl_capi.cc	cxxrtl: implement debug information outlining.	2020-12-14 01:27:27 +00:00
cxxrtl_capi.h	cxxrtl: use `static inline` instead of `inline` in the C API.	2020-12-20 14:48:16 +00:00
cxxrtl_vcd.h	cxxrtl: escape colon in variable names in VCD writer.	2021-07-19 16:22:55 +00:00
cxxrtl_vcd_capi.cc	cxxrtl: add missing namespace.	2020-06-09 06:26:43 +00:00
cxxrtl_vcd_capi.h	Fix formatting. NFC.	2020-06-10 15:48:40 +00:00