mirror of https://github.com/YosysHQ/yosys.git
270 lines
8.4 KiB
C++
270 lines
8.4 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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#include "kernel/celltypes.h"
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#include "kernel/utils.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct CheckPass : public Pass {
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CheckPass() : Pass("check", "check for obvious problems in the design") { }
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void help() YS_OVERRIDE
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" check [options] [selection]\n");
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log("\n");
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log("This pass identifies the following problems in the current design:\n");
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log("\n");
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log(" - combinatorial loops\n");
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log("\n");
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log(" - two or more conflicting drivers for one wire\n");
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log("\n");
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log(" - used wires that do not have a driver\n");
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log("\n");
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log("Options:\n");
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log("\n");
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log(" -noinit\n");
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log(" Also check for wires which have the 'init' attribute set.\n");
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log("\n");
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log(" -initdrv\n");
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log(" Also check for wires that have the 'init' attribute set and are not\n");
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log(" driven by an FF cell type.\n");
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log("\n");
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log(" -mapped\n");
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log(" Also check for internal cells that have not been mapped to cells of the\n");
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log(" target architecture.\n");
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log("\n");
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log(" -allow-tbuf\n");
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log(" Modify the -mapped behavior to still allow $_TBUF_ cells.\n");
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log("\n");
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log(" -assert\n");
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log(" Produce a runtime error if any problems are found in the current design.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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{
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int counter = 0;
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bool noinit = false;
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bool initdrv = false;
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bool mapped = false;
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bool allow_tbuf = false;
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bool assert_mode = false;
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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if (args[argidx] == "-noinit") {
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noinit = true;
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continue;
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}
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if (args[argidx] == "-initdrv") {
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initdrv = true;
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continue;
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}
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if (args[argidx] == "-mapped") {
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mapped = true;
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continue;
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}
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if (args[argidx] == "-allow-tbuf") {
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allow_tbuf = true;
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continue;
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}
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if (args[argidx] == "-assert") {
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assert_mode = true;
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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log_header(design, "Executing CHECK pass (checking for obvious problems).\n");
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pool<IdString> fftypes;
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fftypes.insert(ID($sr));
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fftypes.insert(ID($ff));
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fftypes.insert(ID($dff));
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fftypes.insert(ID($dffe));
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fftypes.insert(ID($dffsr));
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fftypes.insert(ID($adff));
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fftypes.insert(ID($dlatch));
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fftypes.insert(ID($dlatchsr));
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fftypes.insert(ID($_DFFE_NN_));
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fftypes.insert(ID($_DFFE_NP_));
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fftypes.insert(ID($_DFFE_PN_));
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fftypes.insert(ID($_DFFE_PP_));
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fftypes.insert(ID($_DFFSR_NNN_));
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fftypes.insert(ID($_DFFSR_NNP_));
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fftypes.insert(ID($_DFFSR_NPN_));
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fftypes.insert(ID($_DFFSR_NPP_));
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fftypes.insert(ID($_DFFSR_PNN_));
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fftypes.insert(ID($_DFFSR_PNP_));
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fftypes.insert(ID($_DFFSR_PPN_));
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fftypes.insert(ID($_DFFSR_PPP_));
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fftypes.insert(ID($_DFF_NN0_));
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fftypes.insert(ID($_DFF_NN1_));
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fftypes.insert(ID($_DFF_NP0_));
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fftypes.insert(ID($_DFF_NP1_));
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fftypes.insert(ID($_DFF_N_));
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fftypes.insert(ID($_DFF_PN0_));
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fftypes.insert(ID($_DFF_PN1_));
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fftypes.insert(ID($_DFF_PP0_));
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fftypes.insert(ID($_DFF_PP1_));
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fftypes.insert(ID($_DFF_P_));
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fftypes.insert(ID($_DLATCHSR_NNN_));
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fftypes.insert(ID($_DLATCHSR_NNP_));
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fftypes.insert(ID($_DLATCHSR_NPN_));
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fftypes.insert(ID($_DLATCHSR_NPP_));
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fftypes.insert(ID($_DLATCHSR_PNN_));
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fftypes.insert(ID($_DLATCHSR_PNP_));
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fftypes.insert(ID($_DLATCHSR_PPN_));
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fftypes.insert(ID($_DLATCHSR_PPP_));
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fftypes.insert(ID($_DLATCH_N_));
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fftypes.insert(ID($_DLATCH_P_));
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fftypes.insert(ID($_FF_));
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for (auto module : design->selected_whole_modules_warn())
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{
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if (module->has_processes_warn())
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continue;
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log("checking module %s..\n", log_id(module));
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SigMap sigmap(module);
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dict<SigBit, vector<string>> wire_drivers;
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dict<SigBit, int> wire_drivers_count;
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pool<SigBit> used_wires;
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TopoSort<string> topo;
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for (auto cell : module->cells())
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{
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if (mapped && cell->type.begins_with("$") && design->module(cell->type) == nullptr) {
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if (allow_tbuf && cell->type == ID($_TBUF_)) goto cell_allowed;
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log_warning("Cell %s.%s is an unmapped internal cell of type %s.\n", log_id(module), log_id(cell), log_id(cell->type));
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counter++;
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cell_allowed:;
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}
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for (auto &conn : cell->connections()) {
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SigSpec sig = sigmap(conn.second);
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bool logic_cell = yosys_celltypes.cell_evaluable(cell->type);
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if (cell->input(conn.first))
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for (auto bit : sig)
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if (bit.wire) {
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if (logic_cell)
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topo.edge(stringf("wire %s", log_signal(bit)),
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stringf("cell %s (%s)", log_id(cell), log_id(cell->type)));
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used_wires.insert(bit);
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}
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if (cell->output(conn.first))
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for (int i = 0; i < GetSize(sig); i++) {
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if (logic_cell)
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topo.edge(stringf("cell %s (%s)", log_id(cell), log_id(cell->type)),
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stringf("wire %s", log_signal(sig[i])));
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if (sig[i].wire)
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wire_drivers[sig[i]].push_back(stringf("port %s[%d] of cell %s (%s)",
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log_id(conn.first), i, log_id(cell), log_id(cell->type)));
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}
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if (!cell->input(conn.first) && cell->output(conn.first))
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for (auto bit : sig)
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if (bit.wire) wire_drivers_count[bit]++;
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}
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}
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pool<SigBit> init_bits;
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for (auto wire : module->wires()) {
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if (wire->port_input) {
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SigSpec sig = sigmap(wire);
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for (int i = 0; i < GetSize(sig); i++)
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wire_drivers[sig[i]].push_back(stringf("module input %s[%d]", log_id(wire), i));
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}
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if (wire->port_output)
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for (auto bit : sigmap(wire))
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if (bit.wire) used_wires.insert(bit);
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if (wire->port_input && !wire->port_output)
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for (auto bit : sigmap(wire))
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if (bit.wire) wire_drivers_count[bit]++;
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if (wire->attributes.count(ID::init)) {
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Const initval = wire->attributes.at(ID::init);
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for (int i = 0; i < GetSize(initval) && i < GetSize(wire); i++)
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if (initval[i] == State::S0 || initval[i] == State::S1)
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init_bits.insert(sigmap(SigBit(wire, i)));
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if (noinit) {
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log_warning("Wire %s.%s has an unprocessed 'init' attribute.\n", log_id(module), log_id(wire));
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counter++;
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}
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}
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}
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for (auto it : wire_drivers)
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if (wire_drivers_count[it.first] > 1) {
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string message = stringf("multiple conflicting drivers for %s.%s:\n", log_id(module), log_signal(it.first));
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for (auto str : it.second)
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message += stringf(" %s\n", str.c_str());
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log_warning("%s", message.c_str());
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counter++;
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}
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for (auto bit : used_wires)
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if (!wire_drivers.count(bit)) {
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log_warning("Wire %s.%s is used but has no driver.\n", log_id(module), log_signal(bit));
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counter++;
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}
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topo.sort();
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for (auto &loop : topo.loops) {
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string message = stringf("found logic loop in module %s:\n", log_id(module));
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for (auto &str : loop)
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message += stringf(" %s\n", str.c_str());
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log_warning("%s", message.c_str());
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counter++;
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}
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if (initdrv)
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{
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for (auto cell : module->cells())
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{
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if (fftypes.count(cell->type) == 0)
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continue;
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for (auto bit : sigmap(cell->getPort(ID::Q)))
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init_bits.erase(bit);
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}
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SigSpec init_sig(init_bits);
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init_sig.sort_and_unify();
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for (auto chunk : init_sig.chunks()) {
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log_warning("Wire %s.%s has 'init' attribute and is not driven by an FF cell.\n", log_id(module), log_signal(chunk));
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counter++;
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}
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}
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}
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log("found and reported %d problems.\n", counter);
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if (assert_mode && counter > 0)
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log_error("Found %d problems in 'check -assert'.\n", counter);
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}
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} CheckPass;
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PRIVATE_NAMESPACE_END
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