riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
yosys/backends/verilog
History
Clifford Wolf c094c53de8 Removed RTLIL::SigSpec::optimize() 2014-07-23 20:32:28 +02:00
..
Makefile.inc initial import 2013-01-05 11:13:26 +01:00
verilog_backend.cc Removed RTLIL::SigSpec::optimize() 2014-07-23 20:32:28 +02:00
verilog_backend.h initial import 2013-01-05 11:13:26 +01:00