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27 lines
628 B
Plaintext
27 lines
628 B
Plaintext
read_verilog -icells -formal <<EOT
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module top(input CI, I0, output [1:0] CO, output O);
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wire A = 1'b0, B = 1'b0;
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\$__ICE40_CARRY_WRAPPER #(
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// A[0]: 1010 1010 1010 1010
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// A[1]: 1100 1100 1100 1100
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// A[2]: 1111 0000 1111 0000
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// A[3]: 1111 1111 0000 0000
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.LUT(~16'b 0110_1001_1001_0110)
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) u0 (
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.A(A),
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.B(B),
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.CI(CI),
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.I0(I0),
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.I3(CI),
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.CO(CO[0]),
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.O(O)
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);
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SB_CARRY u1 (.I0(~A), .I1(~B), .CI(CI), .CO(CO[1]));
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endmodule
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EOT
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equiv_opt -assert -map +/ice40/cells_map.v -map +/ice40/cells_sim.v ice40_opt
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design -load postopt
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select -assert-count 1 t:*
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select -assert-count 1 t:$lut
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