yosys/frontends/verilog
Lukasz Dalek 7e83a51fc9 Support logic typed parameters
Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
2020-07-06 09:18:48 +02:00
..
.gitignore Add "make coverage" 2018-08-27 14:22:21 +02:00
Makefile.inc Add one mode dependency 2020-03-19 16:53:40 +01:00
const2ast.cc Replacing log_error for log_file_error due consistency 2020-03-31 12:01:29 -06:00
preproc.cc MSVC does not understand __builtin_unreachable 2020-06-17 15:10:08 +02:00
preproc.h Add support for SystemVerilog-style `define to Verilog frontend 2020-03-27 16:08:26 +00:00
verilog_frontend.cc Use C++11 final/override keywords. 2020-06-18 23:34:52 +00:00
verilog_frontend.h frontend: cleanup to use more ID::*, more dict<> instead of map<> 2020-05-04 10:48:37 -07:00
verilog_lexer.l Merge pull request #2179 from splhack/static-cast 2020-07-01 16:40:20 +02:00
verilog_parser.y Support logic typed parameters 2020-07-06 09:18:48 +02:00