mirror of https://github.com/YosysHQ/yosys.git
109 lines
2.9 KiB
Plaintext
109 lines
2.9 KiB
Plaintext
pattern shiftmul_right
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//
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// Optimize mul+shift pairs that result from expressions such as foo[s*W+:W]
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//
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match shift
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select shift->type.in($shift, $shiftx, $shr)
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filter !port(shift, \B).empty()
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endmatch
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// the right shift amount
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state <SigSpec> shift_amount
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// log2 scale factor in interpreting of shift_amount
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// due to zero padding on the shift cell's B port
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state <int> log2scale
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code shift_amount log2scale
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shift_amount = port(shift, \B);
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if (shift->type.in($shr) || !param(shift, \B_SIGNED).as_bool())
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shift_amount.append(State::S0);
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// at this point shift_amount is signed, make
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// sure we can never go negative
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if (shift_amount.bits().back() != State::S0)
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reject;
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while (shift_amount.bits().back() == State::S0) {
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shift_amount.remove(GetSize(shift_amount) - 1);
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if (shift_amount.empty()) reject;
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}
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log2scale = 0;
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while (shift_amount[0] == State::S0) {
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shift_amount.remove(0);
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if (shift_amount.empty()) reject;
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log2scale++;
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}
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if (GetSize(shift_amount) > 20)
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reject;
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endcode
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state <SigSpec> mul_din
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state <Const> mul_const
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match mul
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select mul->type.in($mul)
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index <SigSpec> port(mul, \Y) === shift_amount
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filter !param(mul, \A_SIGNED).as_bool()
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choice <IdString> constport {\A, \B}
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filter port(mul, constport).is_fully_const()
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define <IdString> varport (constport == \A ? \B : \A)
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set mul_const SigSpec({port(mul, constport), SigSpec(State::S0, log2scale)}).as_const()
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// get mul_din unmapped (so no `port()` shorthand)
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// because we will be using it to set the \A port
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// on the shift cell, and we want to stay close
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// to the original design
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set mul_din mul->getPort(varport)
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endmatch
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code
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{
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if (mul_const.empty() || GetSize(mul_const) > 20)
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reject;
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// make sure there's no overlap in the signal
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// selections by the shiftmul pattern
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if (GetSize(port(shift, \Y)) > mul_const.as_int())
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reject;
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int factor_bits = ceil_log2(mul_const.as_int());
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// make sure the multiplication never wraps around
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if (GetSize(shift_amount) + log2scale < factor_bits + GetSize(mul_din))
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reject;
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did_something = true;
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log("right shiftmul pattern in %s: shift=%s, mul=%s\n", log_id(module), log_id(shift), log_id(mul));
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int const_factor = mul_const.as_int();
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int new_const_factor = 1 << factor_bits;
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SigSpec padding(State::Sx, new_const_factor-const_factor);
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SigSpec old_a = port(shift, \A), new_a;
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for (int i = 0; i*const_factor < GetSize(old_a); i++) {
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if ((i+1)*const_factor < GetSize(old_a)) {
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SigSpec slice = old_a.extract(i*const_factor, const_factor);
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new_a.append(slice);
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new_a.append(padding);
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} else {
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new_a.append(old_a.extract_end(i*const_factor));
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}
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}
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SigSpec new_b = {mul_din, SigSpec(State::S0, factor_bits)};
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if (param(shift, \B_SIGNED).as_bool())
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new_b.append(State::S0);
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shift->setPort(\A, new_a);
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shift->setParam(\A_WIDTH, GetSize(new_a));
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shift->setPort(\B, new_b);
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shift->setParam(\B_WIDTH, GetSize(new_b));
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blacklist(shift);
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accept;
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}
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endcode
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