mirror of https://github.com/YosysHQ/yosys.git
1410 lines
26 KiB
Verilog
1410 lines
26 KiB
Verilog
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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* ---
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*
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* The internal logic cell technology mapper.
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*
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* This verilog library contains the mapping of internal cells (e.g. $not with
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* variable bit width) to the internal logic cells (such as the single bit $_INV_
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* gate). Usually this logic network is then mapped to the actual technology
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* using e.g. the "abc" pass.
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*
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* Note that this library does not map $mem cells. They must be mapped to logic
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* and $dff cells using the "memory_map" pass first. (Or map it to custom cells,
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* which is of course highly recommended for larger memories.)
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*
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*/
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// --------------------------------------------------------
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module \$not (A, Y);
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parameter A_SIGNED = 0;
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parameter A_WIDTH = 1;
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parameter Y_WIDTH = 1;
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input [A_WIDTH-1:0] A;
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output [Y_WIDTH-1:0] Y;
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genvar i;
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generate
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for (i = 0; i < Y_WIDTH; i = i + 1) begin:V
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if (i < A_WIDTH) begin
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\$_INV_ gate (
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.A(A[i]),
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.Y(Y[i])
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);
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end else begin
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assign Y[i] = 0;
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end
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end
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endgenerate
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endmodule
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// --------------------------------------------------------
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module \$pos (A, Y);
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parameter A_SIGNED = 0;
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parameter A_WIDTH = 1;
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parameter Y_WIDTH = 1;
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input [A_WIDTH-1:0] A;
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output [Y_WIDTH-1:0] Y;
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genvar i;
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generate
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for (i = 0; i < Y_WIDTH; i = i + 1) begin:V
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if (i < A_WIDTH) begin
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assign Y[i] = A[i];
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end else if (A_SIGNED) begin
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assign Y[i] = A[A_WIDTH-1];
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end else begin
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assign Y[i] = 0;
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end
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end
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endgenerate
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endmodule
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// --------------------------------------------------------
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module \$neg (A, Y);
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parameter A_SIGNED = 0;
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parameter A_WIDTH = 1;
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parameter Y_WIDTH = 1;
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input [A_WIDTH-1:0] A;
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output [Y_WIDTH-1:0] Y;
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\$sub #(
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.A_SIGNED(A_SIGNED),
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.B_SIGNED(A_SIGNED),
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.A_WIDTH(1),
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.B_WIDTH(A_WIDTH),
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.Y_WIDTH(Y_WIDTH)
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) sub (
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.A(0),
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.B(A),
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.Y(Y)
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);
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endmodule
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// --------------------------------------------------------
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module \$and (A, B, Y);
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter A_WIDTH = 1;
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parameter B_WIDTH = 1;
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parameter Y_WIDTH = 1;
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input [A_WIDTH-1:0] A;
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input [B_WIDTH-1:0] B;
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output [Y_WIDTH-1:0] Y;
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wire [Y_WIDTH-1:0] A_buf, B_buf;
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\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
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\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
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genvar i;
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generate
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for (i = 0; i < Y_WIDTH; i = i + 1) begin:V
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\$_AND_ gate (
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.A(A_buf[i]),
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.B(B_buf[i]),
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.Y(Y[i])
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);
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end
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endgenerate
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endmodule
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// --------------------------------------------------------
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module \$or (A, B, Y);
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter A_WIDTH = 1;
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parameter B_WIDTH = 1;
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parameter Y_WIDTH = 1;
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input [A_WIDTH-1:0] A;
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input [B_WIDTH-1:0] B;
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output [Y_WIDTH-1:0] Y;
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wire [Y_WIDTH-1:0] A_buf, B_buf;
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\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
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\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
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genvar i;
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generate
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for (i = 0; i < Y_WIDTH; i = i + 1) begin:V
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\$_OR_ gate (
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.A(A_buf[i]),
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.B(B_buf[i]),
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.Y(Y[i])
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);
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end
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endgenerate
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endmodule
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// --------------------------------------------------------
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module \$xor (A, B, Y);
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter A_WIDTH = 1;
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parameter B_WIDTH = 1;
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parameter Y_WIDTH = 1;
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input [A_WIDTH-1:0] A;
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input [B_WIDTH-1:0] B;
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output [Y_WIDTH-1:0] Y;
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wire [Y_WIDTH-1:0] A_buf, B_buf;
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\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
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\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
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genvar i;
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generate
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for (i = 0; i < Y_WIDTH; i = i + 1) begin:V
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\$_XOR_ gate (
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.A(A_buf[i]),
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.B(B_buf[i]),
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.Y(Y[i])
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);
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end
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endgenerate
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endmodule
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// --------------------------------------------------------
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module \$xnor (A, B, Y);
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter A_WIDTH = 1;
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parameter B_WIDTH = 1;
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parameter Y_WIDTH = 1;
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input [A_WIDTH-1:0] A;
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input [B_WIDTH-1:0] B;
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output [Y_WIDTH-1:0] Y;
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wire [Y_WIDTH-1:0] A_buf, B_buf;
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\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
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\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
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genvar i;
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generate
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for (i = 0; i < Y_WIDTH; i = i + 1) begin:V
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wire tmp;
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\$_XOR_ gate1 (
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.A(A_buf[i]),
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.B(B_buf[i]),
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.Y(tmp)
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);
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\$_INV_ gate2 (
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.A(tmp),
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.Y(Y[i])
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);
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end
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endgenerate
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endmodule
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// --------------------------------------------------------
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module \$reduce_and (A, Y);
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parameter A_SIGNED = 0;
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parameter A_WIDTH = 1;
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parameter Y_WIDTH = 1;
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input [A_WIDTH-1:0] A;
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output Y;
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wire [A_WIDTH-1:0] buffer;
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genvar i;
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generate
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for (i = 1; i < A_WIDTH; i = i + 1) begin:V
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\$_AND_ gate (
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.A(A[i]),
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.B(buffer[i-1]),
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.Y(buffer[i])
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);
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end
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endgenerate
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assign buffer[0] = A[0];
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assign Y = buffer[A_WIDTH-1];
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endmodule
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// --------------------------------------------------------
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module \$reduce_or (A, Y);
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parameter A_SIGNED = 0;
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parameter A_WIDTH = 1;
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parameter Y_WIDTH = 1;
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input [A_WIDTH-1:0] A;
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output Y;
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wire [A_WIDTH-1:0] buffer;
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genvar i;
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generate
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for (i = 1; i < A_WIDTH; i = i + 1) begin:V
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\$_OR_ gate (
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.A(A[i]),
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.B(buffer[i-1]),
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.Y(buffer[i])
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);
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end
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endgenerate
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assign buffer[0] = A[0];
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assign Y = buffer[A_WIDTH-1];
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endmodule
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// --------------------------------------------------------
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module \$reduce_xor (A, Y);
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parameter A_SIGNED = 0;
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parameter A_WIDTH = 1;
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parameter Y_WIDTH = 1;
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input [A_WIDTH-1:0] A;
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output Y;
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wire [A_WIDTH-1:0] buffer;
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genvar i;
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generate
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for (i = 1; i < A_WIDTH; i = i + 1) begin:V
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\$_XOR_ gate (
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.A(A[i]),
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.B(buffer[i-1]),
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.Y(buffer[i])
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);
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end
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endgenerate
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assign buffer[0] = A[0];
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assign Y = buffer[A_WIDTH-1];
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endmodule
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// --------------------------------------------------------
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module \$reduce_xnor (A, Y);
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parameter A_SIGNED = 0;
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parameter A_WIDTH = 1;
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parameter Y_WIDTH = 1;
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input [A_WIDTH-1:0] A;
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output Y;
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wire [A_WIDTH-1:0] buffer;
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genvar i;
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generate
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for (i = 1; i < A_WIDTH; i = i + 1) begin:V
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\$_XOR_ gate (
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.A(A[i]),
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.B(buffer[i-1]),
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.Y(buffer[i])
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);
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end
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endgenerate
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assign buffer[0] = A[0];
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\$_INV_ gate_inv (
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.A(buffer[A_WIDTH-1]),
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.Y(Y)
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);
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endmodule
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// --------------------------------------------------------
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module \$reduce_bool (A, Y);
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parameter A_SIGNED = 0;
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parameter A_WIDTH = 1;
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parameter Y_WIDTH = 1;
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input [A_WIDTH-1:0] A;
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output Y;
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wire [A_WIDTH-1:0] buffer;
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genvar i;
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generate
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for (i = 1; i < A_WIDTH; i = i + 1) begin:V
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\$_OR_ gate (
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.A(A[i]),
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.B(buffer[i-1]),
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.Y(buffer[i])
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);
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end
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endgenerate
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assign buffer[0] = A[0];
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assign Y = buffer[A_WIDTH-1];
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endmodule
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// --------------------------------------------------------
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module \$shift (X, A, Y);
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parameter WIDTH = 1;
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parameter SHIFT = 0;
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input X;
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input [WIDTH-1:0] A;
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output [WIDTH-1:0] Y;
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genvar i;
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generate
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for (i = 0; i < WIDTH; i = i + 1) begin:V
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if (i+SHIFT < 0) begin
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assign Y[i] = 0;
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end else
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if (i+SHIFT < WIDTH) begin
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assign Y[i] = A[i+SHIFT];
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end else begin
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assign Y[i] = X;
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end
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end
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endgenerate
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endmodule
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// --------------------------------------------------------
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module \$shl (A, B, Y);
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter A_WIDTH = 1;
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parameter B_WIDTH = 1;
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parameter Y_WIDTH = 1;
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parameter WIDTH = Y_WIDTH;
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input [A_WIDTH-1:0] A;
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input [B_WIDTH-1:0] B;
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output [Y_WIDTH-1:0] Y;
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genvar i;
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generate
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wire [WIDTH*(B_WIDTH+1)-1:0] chain;
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\$pos #(
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.A_SIGNED(A_SIGNED),
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.A_WIDTH(A_WIDTH),
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.Y_WIDTH(WIDTH)
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) expand (
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.A(A),
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.Y(chain[WIDTH-1:0])
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);
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assign Y = chain[WIDTH*(B_WIDTH+1)-1 : WIDTH*B_WIDTH];
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for (i = 0; i < B_WIDTH; i = i + 1) begin:V
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wire [WIDTH-1:0] unshifted, shifted, result;
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assign unshifted = chain[WIDTH*i + WIDTH-1 : WIDTH*i];
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assign chain[WIDTH*(i+1) + WIDTH-1 : WIDTH*(i+1)] = result;
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\$shift #(
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.WIDTH(WIDTH),
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.SHIFT(0 - (2 ** i))
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) sh (
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.X(0),
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.A(unshifted),
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.Y(shifted)
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);
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\$mux #(
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.WIDTH(WIDTH)
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) mux (
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.A(unshifted),
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.B(shifted),
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.Y(result),
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.S(B[i])
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);
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end
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endgenerate
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endmodule
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// --------------------------------------------------------
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module \$shr (A, B, Y);
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter A_WIDTH = 1;
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parameter B_WIDTH = 1;
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parameter Y_WIDTH = 1;
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parameter WIDTH = A_WIDTH > Y_WIDTH ? A_WIDTH : Y_WIDTH;
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input [A_WIDTH-1:0] A;
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input [B_WIDTH-1:0] B;
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output [Y_WIDTH-1:0] Y;
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genvar i;
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generate
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wire [WIDTH*(B_WIDTH+1)-1:0] chain;
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\$pos #(
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.A_SIGNED(A_SIGNED),
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.A_WIDTH(A_WIDTH),
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.Y_WIDTH(WIDTH)
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) expand (
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.A(A),
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.Y(chain[WIDTH-1:0])
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);
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assign Y = chain[WIDTH*(B_WIDTH+1)-1 : WIDTH*B_WIDTH];
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for (i = 0; i < B_WIDTH; i = i + 1) begin:V
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wire [WIDTH-1:0] unshifted, shifted, result;
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assign unshifted = chain[WIDTH*i + WIDTH-1 : WIDTH*i];
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assign chain[WIDTH*(i+1) + WIDTH-1 : WIDTH*(i+1)] = result;
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\$shift #(
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.WIDTH(WIDTH),
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.SHIFT(2 ** i)
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) sh (
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.X(0),
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.A(unshifted),
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.Y(shifted)
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);
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\$mux #(
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.WIDTH(WIDTH)
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) mux (
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.A(unshifted),
|
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.B(shifted),
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.Y(result),
|
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.S(B[i])
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);
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end
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endgenerate
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|
|
endmodule
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|
|
// --------------------------------------------------------
|
|
|
|
module \$sshl (A, B, Y);
|
|
|
|
parameter A_SIGNED = 0;
|
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parameter B_SIGNED = 0;
|
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parameter A_WIDTH = 1;
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parameter B_WIDTH = 1;
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parameter Y_WIDTH = 1;
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|
|
|
parameter WIDTH = Y_WIDTH;
|
|
|
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input [A_WIDTH-1:0] A;
|
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input [B_WIDTH-1:0] B;
|
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output [Y_WIDTH-1:0] Y;
|
|
|
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genvar i;
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generate
|
|
wire [WIDTH*(B_WIDTH+1)-1:0] chain;
|
|
\$pos #(
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.A_SIGNED(A_SIGNED),
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.A_WIDTH(A_WIDTH),
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.Y_WIDTH(WIDTH)
|
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) expand (
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.A(A),
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.Y(chain[WIDTH-1:0])
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);
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assign Y = chain[WIDTH*(B_WIDTH+1)-1 : WIDTH*B_WIDTH];
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for (i = 0; i < B_WIDTH; i = i + 1) begin:V
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wire [WIDTH-1:0] unshifted, shifted, result;
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assign unshifted = chain[WIDTH*i + WIDTH-1 : WIDTH*i];
|
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assign chain[WIDTH*(i+1) + WIDTH-1 : WIDTH*(i+1)] = result;
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|
\$shift #(
|
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.WIDTH(WIDTH),
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.SHIFT(0 - (2 ** i))
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) sh (
|
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.X(0),
|
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.A(unshifted),
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.Y(shifted)
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);
|
|
\$mux #(
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.WIDTH(WIDTH)
|
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) mux (
|
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.A(unshifted),
|
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.B(shifted),
|
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.Y(result),
|
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.S(B[i])
|
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);
|
|
end
|
|
endgenerate
|
|
|
|
endmodule
|
|
|
|
// --------------------------------------------------------
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|
|
|
module \$sshr (A, B, Y);
|
|
|
|
parameter A_SIGNED = 0;
|
|
parameter B_SIGNED = 0;
|
|
parameter A_WIDTH = 1;
|
|
parameter B_WIDTH = 1;
|
|
parameter Y_WIDTH = 1;
|
|
|
|
parameter WIDTH = A_WIDTH > Y_WIDTH ? A_WIDTH : Y_WIDTH;
|
|
|
|
input [A_WIDTH-1:0] A;
|
|
input [B_WIDTH-1:0] B;
|
|
output [Y_WIDTH-1:0] Y;
|
|
|
|
genvar i;
|
|
generate
|
|
wire [WIDTH*(B_WIDTH+1)-1:0] chain;
|
|
\$pos #(
|
|
.A_SIGNED(A_SIGNED),
|
|
.A_WIDTH(A_WIDTH),
|
|
.Y_WIDTH(WIDTH)
|
|
) expand (
|
|
.A(A),
|
|
.Y(chain[WIDTH-1:0])
|
|
);
|
|
for (i = 0; i < Y_WIDTH; i = i + 1) begin:Y
|
|
if (i < WIDTH) begin
|
|
assign Y[i] = chain[WIDTH*B_WIDTH + i];
|
|
end else
|
|
if (A_SIGNED) begin
|
|
assign Y[i] = chain[WIDTH*B_WIDTH + WIDTH-1];
|
|
end else begin
|
|
assign Y[i] = 0;
|
|
end
|
|
end
|
|
for (i = 0; i < B_WIDTH; i = i + 1) begin:V
|
|
wire [WIDTH-1:0] unshifted, shifted, result;
|
|
assign unshifted = chain[WIDTH*i + WIDTH-1 : WIDTH*i];
|
|
assign chain[WIDTH*(i+1) + WIDTH-1 : WIDTH*(i+1)] = result;
|
|
\$shift #(
|
|
.WIDTH(WIDTH),
|
|
.SHIFT(2 ** i)
|
|
) sh (
|
|
.X(A_SIGNED && A[A_WIDTH-1]),
|
|
.A(unshifted),
|
|
.Y(shifted)
|
|
);
|
|
\$mux #(
|
|
.WIDTH(WIDTH)
|
|
) mux (
|
|
.A(unshifted),
|
|
.B(shifted),
|
|
.Y(result),
|
|
.S(B[i])
|
|
);
|
|
end
|
|
endgenerate
|
|
|
|
endmodule
|
|
|
|
// --------------------------------------------------------
|
|
|
|
module \$fulladd (A, B, C, X, Y);
|
|
|
|
// {X, Y} = A + B + C
|
|
input A, B, C;
|
|
output X, Y;
|
|
|
|
// {t1, t2} = A + B
|
|
wire t1, t2, t3;
|
|
|
|
\$_AND_ gate1 ( .A(A), .B(B), .Y(t1) );
|
|
\$_XOR_ gate2 ( .A(A), .B(B), .Y(t2) );
|
|
\$_AND_ gate3 ( .A(t2), .B(C), .Y(t3) );
|
|
\$_XOR_ gate4 ( .A(t2), .B(C), .Y(Y) );
|
|
\$_OR_ gate5 ( .A(t1), .B(t3), .Y(X) );
|
|
|
|
endmodule
|
|
|
|
|
|
// --------------------------------------------------------
|
|
|
|
module \$alu (A, B, Cin, Y, Cout, Csign);
|
|
|
|
parameter WIDTH = 1;
|
|
|
|
input [WIDTH-1:0] A, B;
|
|
input Cin;
|
|
|
|
output [WIDTH-1:0] Y;
|
|
output Cout, Csign;
|
|
|
|
wire [WIDTH:0] carry;
|
|
assign carry[0] = Cin;
|
|
assign Cout = carry[WIDTH];
|
|
assign Csign = carry[WIDTH-1];
|
|
|
|
genvar i;
|
|
generate
|
|
for (i = 0; i < WIDTH; i = i + 1) begin:V
|
|
\$fulladd adder (
|
|
.A(A[i]),
|
|
.B(B[i]),
|
|
.C(carry[i]),
|
|
.X(carry[i+1]),
|
|
.Y(Y[i])
|
|
);
|
|
end
|
|
endgenerate
|
|
|
|
endmodule
|
|
|
|
// --------------------------------------------------------
|
|
|
|
module \$lt (A, B, Y);
|
|
|
|
parameter A_SIGNED = 0;
|
|
parameter B_SIGNED = 0;
|
|
parameter A_WIDTH = 1;
|
|
parameter B_WIDTH = 1;
|
|
parameter Y_WIDTH = 1;
|
|
|
|
parameter WIDTH = A_WIDTH > B_WIDTH ? A_WIDTH : B_WIDTH;
|
|
|
|
input [A_WIDTH-1:0] A;
|
|
input [B_WIDTH-1:0] B;
|
|
output Y;
|
|
|
|
wire carry, carry_sign;
|
|
wire [WIDTH-1:0] A_buf, B_buf, Y_buf;
|
|
\$pos #(.A_SIGNED(A_SIGNED && B_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
|
|
\$pos #(.A_SIGNED(A_SIGNED && B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
|
|
|
|
\$alu #(
|
|
.WIDTH(WIDTH)
|
|
) alu (
|
|
.A(A_buf),
|
|
.B(~B_buf),
|
|
.Cin(1'b1),
|
|
.Y(Y_buf),
|
|
.Cout(carry),
|
|
.Csign(carry_sign),
|
|
);
|
|
|
|
// ALU flags
|
|
wire cf, of, zf, sf;
|
|
assign cf = !carry;
|
|
assign of = carry ^ carry_sign;
|
|
assign zf = ~|Y_buf;
|
|
assign sf = Y_buf[WIDTH-1];
|
|
|
|
generate
|
|
if (A_SIGNED && B_SIGNED) begin
|
|
assign Y = of != sf;
|
|
end else begin
|
|
assign Y = cf;
|
|
end
|
|
endgenerate
|
|
|
|
endmodule
|
|
|
|
// --------------------------------------------------------
|
|
|
|
module \$le (A, B, Y);
|
|
|
|
parameter A_SIGNED = 0;
|
|
parameter B_SIGNED = 0;
|
|
parameter A_WIDTH = 1;
|
|
parameter B_WIDTH = 1;
|
|
parameter Y_WIDTH = 1;
|
|
|
|
parameter WIDTH = A_WIDTH > B_WIDTH ? A_WIDTH : B_WIDTH;
|
|
|
|
input [A_WIDTH-1:0] A;
|
|
input [B_WIDTH-1:0] B;
|
|
output Y;
|
|
|
|
wire carry, carry_sign;
|
|
wire [WIDTH-1:0] A_buf, B_buf, Y_buf;
|
|
\$pos #(.A_SIGNED(A_SIGNED && B_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
|
|
\$pos #(.A_SIGNED(A_SIGNED && B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
|
|
|
|
\$alu #(
|
|
.WIDTH(WIDTH)
|
|
) alu (
|
|
.A(A_buf),
|
|
.B(~B_buf),
|
|
.Cin(1'b1),
|
|
.Y(Y_buf),
|
|
.Cout(carry),
|
|
.Csign(carry_sign),
|
|
);
|
|
|
|
// ALU flags
|
|
wire cf, of, zf, sf;
|
|
assign cf = !carry;
|
|
assign of = carry ^ carry_sign;
|
|
assign zf = ~|Y_buf;
|
|
assign sf = Y_buf[WIDTH-1];
|
|
|
|
generate
|
|
if (A_SIGNED && B_SIGNED) begin
|
|
assign Y = zf || (of != sf);
|
|
end else begin
|
|
assign Y = zf || cf;
|
|
end
|
|
endgenerate
|
|
|
|
endmodule
|
|
|
|
// --------------------------------------------------------
|
|
|
|
module \$eq (A, B, Y);
|
|
|
|
parameter A_SIGNED = 0;
|
|
parameter B_SIGNED = 0;
|
|
parameter A_WIDTH = 1;
|
|
parameter B_WIDTH = 1;
|
|
parameter Y_WIDTH = 1;
|
|
|
|
parameter WIDTH = A_WIDTH > B_WIDTH ? A_WIDTH : B_WIDTH;
|
|
|
|
input [A_WIDTH-1:0] A;
|
|
input [B_WIDTH-1:0] B;
|
|
output Y;
|
|
|
|
wire carry, carry_sign;
|
|
wire [WIDTH-1:0] A_buf, B_buf, Y_buf;
|
|
\$pos #(.A_SIGNED(A_SIGNED && B_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
|
|
\$pos #(.A_SIGNED(A_SIGNED && B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
|
|
|
|
assign Y = ~|(A_buf ^ B_buf);
|
|
|
|
endmodule
|
|
|
|
// --------------------------------------------------------
|
|
|
|
module \$ne (A, B, Y);
|
|
|
|
parameter A_SIGNED = 0;
|
|
parameter B_SIGNED = 0;
|
|
parameter A_WIDTH = 1;
|
|
parameter B_WIDTH = 1;
|
|
parameter Y_WIDTH = 1;
|
|
|
|
parameter WIDTH = A_WIDTH > B_WIDTH ? A_WIDTH : B_WIDTH;
|
|
|
|
input [A_WIDTH-1:0] A;
|
|
input [B_WIDTH-1:0] B;
|
|
output Y;
|
|
|
|
wire carry, carry_sign;
|
|
wire [WIDTH-1:0] A_buf, B_buf, Y_buf;
|
|
\$pos #(.A_SIGNED(A_SIGNED && B_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
|
|
\$pos #(.A_SIGNED(A_SIGNED && B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
|
|
|
|
assign Y = |(A_buf ^ B_buf);
|
|
|
|
endmodule
|
|
|
|
// --------------------------------------------------------
|
|
|
|
module \$ge (A, B, Y);
|
|
|
|
parameter A_SIGNED = 0;
|
|
parameter B_SIGNED = 0;
|
|
parameter A_WIDTH = 1;
|
|
parameter B_WIDTH = 1;
|
|
parameter Y_WIDTH = 1;
|
|
|
|
input [A_WIDTH-1:0] A;
|
|
input [B_WIDTH-1:0] B;
|
|
output Y;
|
|
|
|
\$le #(
|
|
.A_SIGNED(B_SIGNED),
|
|
.B_SIGNED(A_SIGNED),
|
|
.A_WIDTH(B_WIDTH),
|
|
.B_WIDTH(A_WIDTH)
|
|
) ge_via_le (
|
|
.A(B),
|
|
.B(A),
|
|
.Y(Y)
|
|
);
|
|
|
|
endmodule
|
|
|
|
// --------------------------------------------------------
|
|
|
|
module \$gt (A, B, Y);
|
|
|
|
parameter A_SIGNED = 0;
|
|
parameter B_SIGNED = 0;
|
|
parameter A_WIDTH = 1;
|
|
parameter B_WIDTH = 1;
|
|
parameter Y_WIDTH = 1;
|
|
|
|
input [A_WIDTH-1:0] A;
|
|
input [B_WIDTH-1:0] B;
|
|
output Y;
|
|
|
|
\$lt #(
|
|
.A_SIGNED(B_SIGNED),
|
|
.B_SIGNED(A_SIGNED),
|
|
.A_WIDTH(B_WIDTH),
|
|
.B_WIDTH(A_WIDTH)
|
|
) gt_via_lt (
|
|
.A(B),
|
|
.B(A),
|
|
.Y(Y)
|
|
);
|
|
|
|
endmodule
|
|
|
|
// --------------------------------------------------------
|
|
|
|
module \$add (A, B, Y);
|
|
|
|
parameter A_SIGNED = 0;
|
|
parameter B_SIGNED = 0;
|
|
parameter A_WIDTH = 1;
|
|
parameter B_WIDTH = 1;
|
|
parameter Y_WIDTH = 1;
|
|
|
|
input [A_WIDTH-1:0] A;
|
|
input [B_WIDTH-1:0] B;
|
|
output [Y_WIDTH-1:0] Y;
|
|
|
|
wire [Y_WIDTH-1:0] A_buf, B_buf;
|
|
\$pos #(.A_SIGNED(A_SIGNED && B_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
|
|
\$pos #(.A_SIGNED(A_SIGNED && B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
|
|
|
|
\$alu #(
|
|
.WIDTH(Y_WIDTH)
|
|
) alu (
|
|
.A(A_buf),
|
|
.B(B_buf),
|
|
.Cin(1'b0),
|
|
.Y(Y)
|
|
);
|
|
|
|
endmodule
|
|
|
|
// --------------------------------------------------------
|
|
|
|
module \$sub (A, B, Y);
|
|
|
|
parameter A_SIGNED = 0;
|
|
parameter B_SIGNED = 0;
|
|
parameter A_WIDTH = 1;
|
|
parameter B_WIDTH = 1;
|
|
parameter Y_WIDTH = 1;
|
|
|
|
input [A_WIDTH-1:0] A;
|
|
input [B_WIDTH-1:0] B;
|
|
output [Y_WIDTH-1:0] Y;
|
|
|
|
wire [Y_WIDTH-1:0] A_buf, B_buf;
|
|
\$pos #(.A_SIGNED(A_SIGNED && B_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
|
|
\$pos #(.A_SIGNED(A_SIGNED && B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
|
|
|
|
\$alu #(
|
|
.WIDTH(Y_WIDTH)
|
|
) alu (
|
|
.A(A_buf),
|
|
.B(~B_buf),
|
|
.Cin(1'b1),
|
|
.Y(Y)
|
|
);
|
|
|
|
endmodule
|
|
|
|
// --------------------------------------------------------
|
|
|
|
module \$arraymul (A, B, Y);
|
|
|
|
parameter WIDTH = 8;
|
|
input [WIDTH-1:0] A, B;
|
|
output [WIDTH-1:0] Y;
|
|
|
|
wire [WIDTH*WIDTH-1:0] partials;
|
|
|
|
genvar i;
|
|
assign partials[WIDTH-1 : 0] = A[0] ? B : 0;
|
|
generate for (i = 1; i < WIDTH; i = i+1) begin:gen
|
|
assign partials[WIDTH*(i+1)-1 : WIDTH*i] = (A[i] ? B << i : 0) + partials[WIDTH*i-1 : WIDTH*(i-1)];
|
|
end endgenerate
|
|
|
|
assign Y = partials[WIDTH*WIDTH-1 : WIDTH*(WIDTH-1)];
|
|
|
|
endmodule
|
|
|
|
// --------------------------------------------------------
|
|
|
|
module \$mul (A, B, Y);
|
|
|
|
parameter A_SIGNED = 0;
|
|
parameter B_SIGNED = 0;
|
|
parameter A_WIDTH = 1;
|
|
parameter B_WIDTH = 1;
|
|
parameter Y_WIDTH = 1;
|
|
|
|
input [A_WIDTH-1:0] A;
|
|
input [B_WIDTH-1:0] B;
|
|
output [Y_WIDTH-1:0] Y;
|
|
|
|
wire signed [Y_WIDTH:0] buffer_a = A_SIGNED ? $signed(A) : A;
|
|
wire signed [Y_WIDTH:0] buffer_b = B_SIGNED ? $signed(B) : B;
|
|
|
|
\$arraymul #(
|
|
.WIDTH(Y_WIDTH)
|
|
) arraymul (
|
|
.A(buffer_a),
|
|
.B(buffer_b),
|
|
.Y(Y)
|
|
);
|
|
|
|
endmodule
|
|
|
|
/****
|
|
// --------------------------------------------------------
|
|
|
|
module \$div (A, B, Y);
|
|
|
|
parameter A_SIGNED = 0;
|
|
parameter B_SIGNED = 0;
|
|
parameter A_WIDTH = 1;
|
|
parameter B_WIDTH = 1;
|
|
parameter Y_WIDTH = 1;
|
|
|
|
input [A_WIDTH-1:0] A;
|
|
input [B_WIDTH-1:0] B;
|
|
output [Y_WIDTH-1:0] Y;
|
|
|
|
wire signed [A_WIDTH:0] buffer_a = A_SIGNED ? $signed(A) : A;
|
|
wire signed [B_WIDTH:0] buffer_b = B_SIGNED ? $signed(B) : B;
|
|
|
|
assign Y = buffer_a / buffer_b;
|
|
|
|
endmodule
|
|
|
|
// --------------------------------------------------------
|
|
|
|
module \$mod (A, B, Y);
|
|
|
|
parameter A_SIGNED = 0;
|
|
parameter B_SIGNED = 0;
|
|
parameter A_WIDTH = 1;
|
|
parameter B_WIDTH = 1;
|
|
parameter Y_WIDTH = 1;
|
|
|
|
input [A_WIDTH-1:0] A;
|
|
input [B_WIDTH-1:0] B;
|
|
output [Y_WIDTH-1:0] Y;
|
|
|
|
wire signed [A_WIDTH:0] buffer_a = A_SIGNED ? $signed(A) : A;
|
|
wire signed [B_WIDTH:0] buffer_b = B_SIGNED ? $signed(B) : B;
|
|
|
|
assign Y = buffer_a % buffer_b;
|
|
|
|
endmodule
|
|
|
|
// --------------------------------------------------------
|
|
|
|
module \$pow (A, B, Y);
|
|
|
|
parameter A_SIGNED = 0;
|
|
parameter B_SIGNED = 0;
|
|
parameter A_WIDTH = 1;
|
|
parameter B_WIDTH = 1;
|
|
parameter Y_WIDTH = 1;
|
|
|
|
input [A_WIDTH-1:0] A;
|
|
input [B_WIDTH-1:0] B;
|
|
output [Y_WIDTH-1:0] Y;
|
|
|
|
wire signed [A_WIDTH:0] buffer_a = A_SIGNED ? $signed(A) : A;
|
|
wire signed [B_WIDTH:0] buffer_b = B_SIGNED ? $signed(B) : B;
|
|
|
|
assign Y = buffer_a ** buffer_b;
|
|
|
|
endmodule
|
|
|
|
// --------------------------------------------------------
|
|
****/
|
|
|
|
module \$logic_not (A, Y);
|
|
|
|
parameter A_SIGNED = 0;
|
|
parameter A_WIDTH = 1;
|
|
parameter Y_WIDTH = 1;
|
|
|
|
input [A_WIDTH-1:0] A;
|
|
output [Y_WIDTH-1:0] Y;
|
|
|
|
wire A_buf;
|
|
|
|
\$reduce_bool #(
|
|
.A_SIGNED(A_SIGNED),
|
|
.A_WIDTH(A_WIDTH)
|
|
) A_logic (
|
|
.A(A),
|
|
.Y(A_buf)
|
|
);
|
|
|
|
\$_INV_ gate (
|
|
.A(A_buf),
|
|
.Y(Y[0])
|
|
);
|
|
|
|
generate
|
|
if (Y_WIDTH > 1) begin:V
|
|
assign Y[Y_WIDTH-1:1] = 0;
|
|
end
|
|
endgenerate
|
|
|
|
endmodule
|
|
|
|
// --------------------------------------------------------
|
|
|
|
module \$logic_and (A, B, Y);
|
|
|
|
parameter A_SIGNED = 0;
|
|
parameter B_SIGNED = 0;
|
|
parameter A_WIDTH = 1;
|
|
parameter B_WIDTH = 1;
|
|
parameter Y_WIDTH = 1;
|
|
|
|
input [A_WIDTH-1:0] A;
|
|
input [B_WIDTH-1:0] B;
|
|
output [Y_WIDTH-1:0] Y;
|
|
|
|
wire A_buf, B_buf;
|
|
|
|
\$reduce_bool #(
|
|
.A_SIGNED(A_SIGNED),
|
|
.A_WIDTH(A_WIDTH)
|
|
) A_logic (
|
|
.A(A),
|
|
.Y(A_buf)
|
|
);
|
|
|
|
\$reduce_bool #(
|
|
.A_SIGNED(B_SIGNED),
|
|
.A_WIDTH(B_WIDTH)
|
|
) B_logic (
|
|
.A(B),
|
|
.Y(B_buf)
|
|
);
|
|
|
|
\$_AND_ gate (
|
|
.A(A_buf),
|
|
.B(B_buf),
|
|
.Y(Y[0])
|
|
);
|
|
|
|
generate
|
|
if (Y_WIDTH > 1) begin:V
|
|
assign Y[Y_WIDTH-1:1] = 0;
|
|
end
|
|
endgenerate
|
|
|
|
endmodule
|
|
|
|
// --------------------------------------------------------
|
|
|
|
module \$logic_or (A, B, Y);
|
|
|
|
parameter A_SIGNED = 0;
|
|
parameter B_SIGNED = 0;
|
|
parameter A_WIDTH = 1;
|
|
parameter B_WIDTH = 1;
|
|
parameter Y_WIDTH = 1;
|
|
|
|
input [A_WIDTH-1:0] A;
|
|
input [B_WIDTH-1:0] B;
|
|
output [Y_WIDTH-1:0] Y;
|
|
|
|
wire A_buf, B_buf;
|
|
|
|
\$reduce_bool #(
|
|
.A_SIGNED(A_SIGNED),
|
|
.A_WIDTH(A_WIDTH)
|
|
) A_logic (
|
|
.A(A),
|
|
.Y(A_buf)
|
|
);
|
|
|
|
\$reduce_bool #(
|
|
.A_SIGNED(B_SIGNED),
|
|
.A_WIDTH(B_WIDTH)
|
|
) B_logic (
|
|
.A(B),
|
|
.Y(B_buf)
|
|
);
|
|
|
|
\$_OR_ gate (
|
|
.A(A_buf),
|
|
.B(B_buf),
|
|
.Y(Y[0])
|
|
);
|
|
|
|
generate
|
|
if (Y_WIDTH > 1) begin:V
|
|
assign Y[Y_WIDTH-1:1] = 0;
|
|
end
|
|
endgenerate
|
|
|
|
endmodule
|
|
|
|
// --------------------------------------------------------
|
|
|
|
module \$mux (A, B, S, Y);
|
|
|
|
parameter WIDTH = 1;
|
|
|
|
input [WIDTH-1:0] A, B;
|
|
input S;
|
|
output [WIDTH-1:0] Y;
|
|
|
|
genvar i;
|
|
generate
|
|
for (i = 0; i < WIDTH; i = i + 1) begin:V
|
|
\$_MUX_ gate (
|
|
.A(A[i]),
|
|
.B(B[i]),
|
|
.S(S),
|
|
.Y(Y[i])
|
|
);
|
|
end
|
|
endgenerate
|
|
|
|
endmodule
|
|
|
|
// --------------------------------------------------------
|
|
|
|
module \$pmux (A, B, S, Y);
|
|
|
|
parameter WIDTH = 1;
|
|
parameter S_WIDTH = 1;
|
|
|
|
input [WIDTH-1:0] A;
|
|
input [WIDTH*S_WIDTH-1:0] B;
|
|
input [S_WIDTH-1:0] S;
|
|
output [WIDTH-1:0] Y;
|
|
|
|
wire [WIDTH-1:0] Y_B;
|
|
|
|
genvar i, j;
|
|
generate
|
|
wire [WIDTH*S_WIDTH-1:0] B_AND_S;
|
|
for (i = 0; i < S_WIDTH; i = i + 1) begin:B_AND
|
|
assign B_AND_S[WIDTH*(i+1)-1:WIDTH*i] = B[WIDTH*(i+1)-1:WIDTH*i] & {WIDTH{S[i]}};
|
|
end:B_AND
|
|
for (i = 0; i < WIDTH; i = i + 1) begin:B_OR
|
|
wire [S_WIDTH-1:0] B_AND_BITS;
|
|
for (j = 0; j < S_WIDTH; j = j + 1) begin:B_AND_BITS_COLLECT
|
|
assign B_AND_BITS[j] = B_AND_S[WIDTH*j+i];
|
|
end:B_AND_BITS_COLLECT
|
|
assign Y_B[i] = |B_AND_BITS;
|
|
end:B_OR
|
|
endgenerate
|
|
|
|
assign Y = |S ? Y_B : A;
|
|
|
|
endmodule
|
|
|
|
// --------------------------------------------------------
|
|
|
|
module \$safe_pmux (A, B, S, Y);
|
|
|
|
parameter WIDTH = 1;
|
|
parameter S_WIDTH = 1;
|
|
|
|
input [WIDTH-1:0] A;
|
|
input [WIDTH*S_WIDTH-1:0] B;
|
|
input [S_WIDTH-1:0] S;
|
|
output [WIDTH-1:0] Y;
|
|
|
|
wire [S_WIDTH-1:0] status_found_first;
|
|
wire [S_WIDTH-1:0] status_found_second;
|
|
|
|
genvar i;
|
|
generate
|
|
for (i = 0; i < S_WIDTH; i = i + 1) begin:GEN1
|
|
wire pre_first;
|
|
if (i > 0) begin:GEN2
|
|
assign pre_first = status_found_first[i-1];
|
|
end:GEN2 else begin:GEN3
|
|
assign pre_first = 0;
|
|
end:GEN3
|
|
assign status_found_first[i] = pre_first | S[i];
|
|
assign status_found_second[i] = pre_first & S[i];
|
|
end:GEN1
|
|
endgenerate
|
|
|
|
\$pmux #(
|
|
.WIDTH(WIDTH),
|
|
.S_WIDTH(S_WIDTH)
|
|
) pmux_cell (
|
|
.A(A),
|
|
.B(B),
|
|
.S(S & {S_WIDTH{~|status_found_second}}),
|
|
.Y(Y)
|
|
);
|
|
|
|
endmodule
|
|
|
|
// --------------------------------------------------------
|
|
|
|
module \$dff (CLK, D, Q);
|
|
|
|
parameter WIDTH = 1;
|
|
parameter CLK_POLARITY = 1'b1;
|
|
|
|
input CLK;
|
|
input [WIDTH-1:0] D;
|
|
output [WIDTH-1:0] Q;
|
|
|
|
genvar i;
|
|
generate
|
|
if (CLK_POLARITY == 0)
|
|
for (i = 0; i < WIDTH; i = i + 1) begin:V
|
|
\$_DFF_N_ ff (
|
|
.D(D[i]),
|
|
.Q(Q[i]),
|
|
.C(CLK)
|
|
);
|
|
end
|
|
if (CLK_POLARITY != 0)
|
|
for (i = 0; i < WIDTH; i = i + 1) begin:V
|
|
\$_DFF_P_ ff (
|
|
.D(D[i]),
|
|
.Q(Q[i]),
|
|
.C(CLK)
|
|
);
|
|
end
|
|
endgenerate
|
|
|
|
endmodule
|
|
|
|
// --------------------------------------------------------
|
|
|
|
module \$adff (CLK, ARST, D, Q);
|
|
|
|
parameter WIDTH = 1;
|
|
parameter CLK_POLARITY = 1'b1;
|
|
parameter ARST_POLARITY = 1'b1;
|
|
parameter ARST_VALUE = 0;
|
|
|
|
input CLK, ARST;
|
|
input [WIDTH-1:0] D;
|
|
output [WIDTH-1:0] Q;
|
|
|
|
genvar i;
|
|
generate
|
|
for (i = 0; i < WIDTH; i = i + 1) begin:V
|
|
if (CLK_POLARITY == 0) begin:N
|
|
if (ARST_POLARITY == 0) begin:NN
|
|
if (ARST_VALUE[i] == 0) begin:NN0
|
|
\$_DFF_NN0_ ff (
|
|
.D(D[i]),
|
|
.Q(Q[i]),
|
|
.C(CLK),
|
|
.R(ARST)
|
|
);
|
|
end else begin:NN1
|
|
\$_DFF_NN1_ ff (
|
|
.D(D[i]),
|
|
.Q(Q[i]),
|
|
.C(CLK),
|
|
.R(ARST)
|
|
);
|
|
end
|
|
end else begin:NP
|
|
if (ARST_VALUE[i] == 0) begin:NP0
|
|
\$_DFF_NP0_ ff (
|
|
.D(D[i]),
|
|
.Q(Q[i]),
|
|
.C(CLK),
|
|
.R(ARST)
|
|
);
|
|
end else begin:NP1
|
|
\$_DFF_NP1_ ff (
|
|
.D(D[i]),
|
|
.Q(Q[i]),
|
|
.C(CLK),
|
|
.R(ARST)
|
|
);
|
|
end
|
|
end
|
|
end else begin:P
|
|
if (ARST_POLARITY == 0) begin:PN
|
|
if (ARST_VALUE[i] == 0) begin:PN0
|
|
\$_DFF_PN0_ ff (
|
|
.D(D[i]),
|
|
.Q(Q[i]),
|
|
.C(CLK),
|
|
.R(ARST)
|
|
);
|
|
end else begin:PN1
|
|
\$_DFF_PN1_ ff (
|
|
.D(D[i]),
|
|
.Q(Q[i]),
|
|
.C(CLK),
|
|
.R(ARST)
|
|
);
|
|
end
|
|
end else begin:PP
|
|
if (ARST_VALUE[i] == 0) begin:PP0
|
|
\$_DFF_PP0_ ff (
|
|
.D(D[i]),
|
|
.Q(Q[i]),
|
|
.C(CLK),
|
|
.R(ARST)
|
|
);
|
|
end else begin:PP1
|
|
\$_DFF_PP1_ ff (
|
|
.D(D[i]),
|
|
.Q(Q[i]),
|
|
.C(CLK),
|
|
.R(ARST)
|
|
);
|
|
end
|
|
end
|
|
end
|
|
end
|
|
endgenerate
|
|
|
|
endmodule
|
|
|
|
// --------------------------------------------------------
|
|
|