mirror of https://github.com/YosysHQ/yosys.git
370 lines
10 KiB
C++
370 lines
10 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2018 whitequark <whitequark@whitequark.org>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "backends/ilang/ilang_backend.h"
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USING_YOSYS_NAMESPACE
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using namespace ILANG_BACKEND;
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PRIVATE_NAMESPACE_BEGIN
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struct BugpointPass : public Pass {
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BugpointPass() : Pass("bugpoint", "minimize testcases") { }
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void help() YS_OVERRIDE
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" bugpoint [options]\n");
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log("\n");
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log("This command minimizes testcases that crash Yosys. It removes an arbitrary part\n");
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log("of the design and recursively invokes Yosys with a given script, repeating these\n");
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log("steps while it can find a smaller design that still causes a crash. Once this\n");
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log("command finishes, it replaces the current design with the smallest testcase it\n");
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log("was able to produce.\n");
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log("\n");
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log("It is possible to specify the kinds of design part that will be removed. If none\n");
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log("are specified, all parts of design will be removed.\n");
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log("\n");
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log(" -yosys <filename>\n");
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log(" use this Yosys binary. if not specified, `yosys` is used.\n");
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log("\n");
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log(" -script <filename>\n");
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log(" use this script to crash Yosys. required.\n");
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log("\n");
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log(" -grep <string>\n");
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log(" only consider crashes that place this string in the log file.\n");
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log("\n");
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log(" -fast\n");
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log(" run `clean -purge` after each minimization step. converges faster, but\n");
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log(" produces larger testcases, and may fail to produce any testcase at all if\n");
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log(" the crash is related to dangling wires.\n");
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log("\n");
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log(" -clean\n");
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log(" run `clean -purge` before checking testcase and after finishing. produces\n");
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log(" smaller and more useful testcases, but may fail to produce any testcase\n");
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log(" at all if the crash is related to dangling wires.\n");
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log("\n");
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log(" -modules\n");
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log(" try to remove modules.\n");
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log("\n");
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log(" -ports\n");
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log(" try to remove module ports.\n");
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log("\n");
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log(" -cells\n");
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log(" try to remove cells.\n");
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log("\n");
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log(" -connections\n");
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log(" try to reconnect ports to 'x.\n");
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log("\n");
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}
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bool run_yosys(RTLIL::Design *design, string yosys_cmd, string script)
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{
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design->sort();
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std::ofstream f("bugpoint-case.il");
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ILANG_BACKEND::dump_design(f, design, /*only_selected=*/false, /*flag_m=*/true, /*flag_n=*/false);
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f.close();
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string yosys_cmdline = stringf("%s -qq -L bugpoint-case.log -s %s bugpoint-case.il", yosys_cmd.c_str(), script.c_str());
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return run_command(yosys_cmdline) == 0;
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}
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bool check_logfile(string grep)
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{
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if (grep.empty())
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return true;
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std::ifstream f("bugpoint-case.log");
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while (!f.eof())
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{
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string line;
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getline(f, line);
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if (line.find(grep) != std::string::npos)
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return true;
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}
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return false;
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}
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RTLIL::Design *clean_design(RTLIL::Design *design, bool do_clean = true, bool do_delete = false)
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{
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if (!do_clean)
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return design;
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RTLIL::Design *design_copy = new RTLIL::Design;
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for (auto &it : design->modules_)
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design_copy->add(it.second->clone());
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Pass::call(design_copy, "clean -purge");
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if (do_delete)
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delete design;
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return design_copy;
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}
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RTLIL::Design *simplify_something(RTLIL::Design *design, int &seed, bool stage2, bool modules, bool ports, bool cells, bool connections)
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{
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RTLIL::Design *design_copy = new RTLIL::Design;
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for (auto &it : design->modules_)
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design_copy->add(it.second->clone());
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int index = 0;
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if (modules)
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{
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for (auto &it : design_copy->modules_)
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{
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if (it.second->get_bool_attribute("\\blackbox"))
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continue;
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if (index++ == seed)
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{
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log("Trying to remove module %s.\n", it.first.c_str());
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design_copy->remove(it.second);
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return design_copy;
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}
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}
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}
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if (ports)
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{
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for (auto mod : design_copy->modules())
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{
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if (mod->get_bool_attribute("\\blackbox"))
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continue;
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for (auto wire : mod->wires())
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{
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if (!stage2 && wire->get_bool_attribute("$bugpoint"))
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continue;
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if (wire->port_input || wire->port_output)
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{
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if (index++ == seed)
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{
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log("Trying to remove module port %s.\n", log_signal(wire));
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wire->port_input = wire->port_output = false;
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mod->fixup_ports();
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return design_copy;
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}
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}
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}
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}
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}
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if (cells)
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{
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for (auto mod : design_copy->modules())
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{
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if (mod->get_bool_attribute("\\blackbox"))
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continue;
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for (auto &it : mod->cells_)
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{
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if (index++ == seed)
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{
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log("Trying to remove cell %s.%s.\n", mod->name.c_str(), it.first.c_str());
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mod->remove(it.second);
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return design_copy;
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}
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}
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}
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}
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if (connections)
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{
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for (auto mod : design_copy->modules())
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{
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if (mod->get_bool_attribute("\\blackbox"))
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continue;
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for (auto cell : mod->cells())
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{
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for (auto it : cell->connections_)
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{
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RTLIL::SigSpec port = cell->getPort(it.first);
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bool is_undef = port.is_fully_undef();
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bool is_port = port.is_wire() && (port.as_wire()->port_input || port.as_wire()->port_output);
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if(is_undef || (!stage2 && is_port))
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continue;
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if (index++ == seed)
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{
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log("Trying to remove cell port %s.%s.%s.\n", mod->name.c_str(), cell->name.c_str(), it.first.c_str());
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RTLIL::SigSpec port_x(State::Sx, port.size());
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cell->unsetPort(it.first);
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cell->setPort(it.first, port_x);
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return design_copy;
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}
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if (!stage2 && (cell->input(it.first) || cell->output(it.first)) && index++ == seed)
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{
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log("Trying to expose cell port %s.%s.%s as module port.\n", mod->name.c_str(), cell->name.c_str(), it.first.c_str());
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RTLIL::Wire *wire = mod->addWire(NEW_ID, port.size());
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wire->set_bool_attribute("$bugpoint");
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wire->port_input = cell->input(it.first);
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wire->port_output = cell->output(it.first);
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cell->unsetPort(it.first);
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cell->setPort(it.first, wire);
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mod->fixup_ports();
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return design_copy;
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}
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}
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}
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}
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}
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return NULL;
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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{
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string yosys_cmd = "yosys", script, grep;
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bool fast = false, clean = false;
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bool modules = false, ports = false, cells = false, connections = false, has_part = false;
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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if (args[argidx] == "-yosys" && argidx + 1 < args.size()) {
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yosys_cmd = args[++argidx];
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continue;
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}
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if (args[argidx] == "-script" && argidx + 1 < args.size()) {
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script = args[++argidx];
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continue;
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}
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if (args[argidx] == "-grep" && argidx + 1 < args.size()) {
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grep = args[++argidx];
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continue;
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}
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if (args[argidx] == "-fast") {
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fast = true;
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continue;
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}
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if (args[argidx] == "-clean") {
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clean = true;
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continue;
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}
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if (args[argidx] == "-modules") {
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modules = true;
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has_part = true;
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continue;
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}
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if (args[argidx] == "-ports") {
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ports = true;
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has_part = true;
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continue;
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}
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if (args[argidx] == "-cells") {
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cells = true;
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has_part = true;
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continue;
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}
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if (args[argidx] == "-connections") {
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connections = true;
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has_part = true;
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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if (!has_part)
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{
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modules = true;
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ports = true;
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cells = true;
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connections = true;
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}
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if (!design->full_selection())
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log_cmd_error("This command only operates on fully selected designs!\n");
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RTLIL::Design *crashing_design = clean_design(design, clean);
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if (run_yosys(crashing_design, yosys_cmd, script))
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log_cmd_error("The provided script file and Yosys binary do not crash on this design!\n");
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if (!check_logfile(grep))
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log_cmd_error("The provided grep string is not found in the log file!\n");
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int seed = 0, crashing_seed = seed;
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bool found_something = false, stage2 = false;
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while (true)
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{
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if (RTLIL::Design *simplified = simplify_something(crashing_design, seed, stage2, modules, ports, cells, connections))
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{
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simplified = clean_design(simplified, fast, /*do_delete=*/true);
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bool crashes;
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if (clean)
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{
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RTLIL::Design *testcase = clean_design(simplified);
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crashes = !run_yosys(testcase, yosys_cmd, script);
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delete testcase;
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}
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else
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{
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crashes = !run_yosys(simplified, yosys_cmd, script);
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}
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if (crashes && check_logfile(grep))
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{
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log("Testcase crashes.\n");
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if (crashing_design != design)
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delete crashing_design;
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crashing_design = simplified;
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crashing_seed = seed;
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found_something = true;
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}
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else
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{
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log("Testcase does not crash.\n");
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delete simplified;
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seed++;
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}
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}
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else
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{
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seed = 0;
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if (found_something)
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found_something = false;
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else
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{
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if (!stage2)
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{
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log("Demoting introduced module ports.\n");
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stage2 = true;
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}
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else
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{
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log("Simplifications exhausted.\n");
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break;
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}
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}
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}
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}
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if (crashing_design != design)
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{
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Pass::call(design, "design -reset");
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crashing_design = clean_design(crashing_design, clean, /*do_delete=*/true);
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for (auto &it : crashing_design->modules_)
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design->add(it.second->clone());
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delete crashing_design;
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}
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}
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} BugpointPass;
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PRIVATE_NAMESPACE_END
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