mirror of https://github.com/YosysHQ/yosys.git
73 lines
1.9 KiB
Plaintext
73 lines
1.9 KiB
Plaintext
pattern muxadd
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//
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// Authored by Akash Levy and Alain Dargelas of Silimate, Inc. under ISC license.
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// Transforms add->mux into mux->add:
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// y = s ? (a + b) : a ===> y = a + (s ? b : 0)
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//
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state <SigSpec> add_a add_b add_y add_a_ext
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state <Const> add_a_signed
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state <IdString> add_a_id add_b_id
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match add
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// Select adder
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select add->type == $add
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choice <IdString> A {\A, \B}
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define <IdString> B (A == \A ? \B : \A)
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set add_y port(add, \Y)
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set add_a port(add, A)
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set add_b port(add, B)
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set add_a_signed param(add, (A == \A) ? \A_SIGNED : \B_SIGNED)
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set add_a_id A
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set add_b_id B
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endmatch
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code add_y add_a add_b add_a_ext
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// Get adder signals
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add_a = port(add, \A);
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add_b = port(add, \B);
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add_y = port(add, \Y);
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add_a_ext = SigSpec(add_a);
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add_a_ext.extend_u0(GetSize(add_y), param(add, \A_SIGNED).as_bool());
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// Fanout of each adder Y bit should be 1 (no bit-split)
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if (nusers(add_y) != 2)
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reject;
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// A and B can be interchanged
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branch;
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std::swap(add_a, add_b);
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endcode
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match mux
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// Select mux of form s ? (a + b) : a, allow leading 0s when A_WIDTH != Y_WIDTH
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select mux->type == $mux
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index <SigSpec> port(mux, \A) === add_a_ext
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index <SigSpec> port(mux, \B) === add_y
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endmatch
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code
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// Get mux signal
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SigSpec mux_y = port(mux, \Y);
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SigSpec mux_a = port(mux, \A);
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SigSpec mux_b = port(mux, \B);
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// Prevent multiple branches to edit the same pair of mux/add
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if (mux_b == add_y || mux_a == add_y) {
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// Create new mid wire
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SigSpec mid = module->addWire(NEW_ID, GetSize(add_b));
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// Rewire
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add->setPort(\B, mid);
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add->setPort(\A, add_a);
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add->setPort(\Y, add_y);
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mux->setPort(add_a_id, Const(State::S0, GetSize(add_b)));
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mux->setPort(add_b_id, add_b);
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mux->setPort(\Y, mid);
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module->connect(mux_y, add_y);
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// Log, fixup, accept
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log("muxadd pattern in %s: mux=%s, add=%s\n", log_id(module), log_id(mux), log_id(add));
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add->fixup_parameters();
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mux->fixup_parameters();
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did_something = true;
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accept;
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}
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endcode
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