mirror of https://github.com/YosysHQ/yosys.git
267 lines
5.7 KiB
Verilog
267 lines
5.7 KiB
Verilog
// Virtex 2, Virtex 2 Pro, Spartan 3, Spartan 3E, Spartan 3A block RAM
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// mapping (Spartan 3A is a superset of the other four).
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// ------------------------------------------------------------------------
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module \$__XILINX_RAMB16 (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
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parameter CFG_ABITS = 9;
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parameter CFG_DBITS = 36;
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parameter CFG_ENABLE_B = 1;
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parameter CLKPOL2 = 1;
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parameter CLKPOL3 = 1;
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parameter [18431:0] INIT = 18432'bx;
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input CLK2;
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input CLK3;
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input [CFG_ABITS-1:0] A1ADDR;
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output [CFG_DBITS-1:0] A1DATA;
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input A1EN;
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input [CFG_ABITS-1:0] B1ADDR;
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input [CFG_DBITS-1:0] B1DATA;
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input [CFG_ENABLE_B-1:0] B1EN;
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generate if (CFG_DBITS == 1) begin
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wire DOB;
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RAMB16_S1_S1 #(
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`include "brams_init_16.vh"
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.WRITE_MODE_A("READ_FIRST"),
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.WRITE_MODE_B("READ_FIRST"),
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) _TECHMAP_REPLACE_ (
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.DIA(1'd0),
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.DOA(A1DATA),
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.ADDRA(A1ADDR),
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.CLKA(CLK2 ^ !CLKPOL2),
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.ENA(A1EN),
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.SSRA(|0),
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.WEA(1'b0),
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.DIB(B1DATA),
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.DOB(DOB),
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.ADDRB(B1ADDR),
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.CLKB(CLK3 ^ !CLKPOL3),
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.ENB(|1),
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.SSRB(|0),
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.WEB(B1EN)
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);
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end else if (CFG_DBITS == 2) begin
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wire [1:0] DOB;
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RAMB16_S2_S2 #(
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`include "brams_init_16.vh"
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.WRITE_MODE_A("READ_FIRST"),
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.WRITE_MODE_B("READ_FIRST"),
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) _TECHMAP_REPLACE_ (
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.DIA(2'd0),
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.DOA(A1DATA),
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.ADDRA(A1ADDR),
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.CLKA(CLK2 ^ !CLKPOL2),
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.ENA(A1EN),
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.SSRA(|0),
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.WEA(1'b0),
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.DIB(B1DATA),
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.DOB(DOB),
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.ADDRB(B1ADDR),
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.CLKB(CLK3 ^ !CLKPOL3),
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.ENB(|1),
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.SSRB(|0),
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.WEB(B1EN)
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);
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end else if (CFG_DBITS == 4) begin
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wire [3:0] DOB;
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RAMB16_S4_S4 #(
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`include "brams_init_16.vh"
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.WRITE_MODE_A("READ_FIRST"),
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.WRITE_MODE_B("READ_FIRST"),
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) _TECHMAP_REPLACE_ (
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.DIA(4'd0),
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.DOA(A1DATA),
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.ADDRA(A1ADDR),
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.CLKA(CLK2 ^ !CLKPOL2),
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.ENA(A1EN),
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.SSRA(|0),
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.WEA(1'b0),
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.DIB(B1DATA),
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.DOB(DOB),
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.ADDRB(B1ADDR),
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.CLKB(CLK3 ^ !CLKPOL3),
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.ENB(|1),
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.SSRB(|0),
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.WEB(B1EN)
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);
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end else if (CFG_DBITS == 9) begin
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wire [7:0] DOB;
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wire DOPB;
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RAMB16_S9_S9 #(
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`include "brams_init_18.vh"
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.WRITE_MODE_A("READ_FIRST"),
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.WRITE_MODE_B("READ_FIRST"),
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) _TECHMAP_REPLACE_ (
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.DIA(8'd0),
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.DIPA(1'd0),
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.DOA(A1DATA[7:0]),
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.DOPA(A1DATA[8]),
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.ADDRA(A1ADDR),
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.CLKA(CLK2 ^ !CLKPOL2),
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.ENA(A1EN),
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.SSRA(|0),
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.WEA(1'b0),
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.DIB(B1DATA[7:0]),
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.DIPB(B1DATA[8]),
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.DOB(DOB),
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.DOPB(DOPB),
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.ADDRB(B1ADDR),
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.CLKB(CLK3 ^ !CLKPOL3),
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.ENB(|1),
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.SSRB(|0),
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.WEB(B1EN)
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);
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end else if (CFG_DBITS == 18) begin
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wire [15:0] DOB;
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wire [1:0] DOPB;
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RAMB16_S18_S18 #(
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`include "brams_init_18.vh"
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.WRITE_MODE_A("READ_FIRST"),
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.WRITE_MODE_B("READ_FIRST"),
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) _TECHMAP_REPLACE_ (
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.DIA(16'd0),
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.DIPA(2'd0),
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.DOA({A1DATA[16:9], A1DATA[7:0]}),
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.DOPA({A1DATA[17], A1DATA[8]}),
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.ADDRA(A1ADDR),
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.CLKA(CLK2 ^ !CLKPOL2),
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.ENA(A1EN),
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.SSRA(|0),
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.WEA(1'b0),
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.DIB({B1DATA[16:9], B1DATA[7:0]}),
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.DIPB({B1DATA[17], B1DATA[8]}),
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.DOB(DOB),
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.DOPB(DOPB),
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.ADDRB(B1ADDR),
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.CLKB(CLK3 ^ !CLKPOL3),
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.ENB(|1),
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.SSRB(|0),
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.WEB(B1EN)
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);
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end else if (CFG_DBITS == 36) begin
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wire [31:0] DOB;
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wire [3:0] DOPB;
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RAMB16_S36_S36 #(
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`include "brams_init_18.vh"
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.WRITE_MODE_A("READ_FIRST"),
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.WRITE_MODE_B("READ_FIRST"),
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) _TECHMAP_REPLACE_ (
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.DIA(32'd0),
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.DIPA(4'd0),
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.DOA({A1DATA[34:27], A1DATA[25:18], A1DATA[16:9], A1DATA[7:0]}),
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.DOPA({A1DATA[35], A1DATA[26], A1DATA[17], A1DATA[8]}),
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.ADDRA(A1ADDR),
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.CLKA(CLK2 ^ !CLKPOL2),
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.ENA(A1EN),
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.SSRA(|0),
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.WEA(1'b0),
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.DIB({B1DATA[34:27], B1DATA[25:18], B1DATA[16:9], B1DATA[7:0]}),
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.DIPB({B1DATA[35], B1DATA[26], B1DATA[17], B1DATA[8]}),
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.DOB(DOB),
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.DOPB(DOPB),
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.ADDRB(B1ADDR),
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.CLKB(CLK3 ^ !CLKPOL3),
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.ENB(|1),
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.SSRB(|0),
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.WEB(B1EN)
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);
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end else begin
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$error("Strange block RAM data width.");
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end endgenerate
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endmodule
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// Version with separate byte enables, only available on Spartan 3A.
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module \$__XILINX_RAMB16BWE (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
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parameter CFG_ABITS = 9;
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parameter CFG_DBITS = 36;
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parameter CFG_ENABLE_B = 4;
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parameter CLKPOL2 = 1;
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parameter CLKPOL3 = 1;
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parameter [18431:0] INIT = 18432'bx;
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input CLK2;
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input CLK3;
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input [CFG_ABITS-1:0] A1ADDR;
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output [CFG_DBITS-1:0] A1DATA;
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input A1EN;
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input [CFG_ABITS-1:0] B1ADDR;
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input [CFG_DBITS-1:0] B1DATA;
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input [CFG_ENABLE_B-1:0] B1EN;
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generate if (CFG_DBITS == 18) begin
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wire [15:0] DOB;
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wire [1:0] DOPB;
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RAMB16BWE_S18_S18 #(
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`include "brams_init_18.vh"
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.WRITE_MODE_A("READ_FIRST"),
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.WRITE_MODE_B("READ_FIRST"),
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) _TECHMAP_REPLACE_ (
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.DIA(16'd0),
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.DIPA(2'd0),
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.DOA({A1DATA[16:9], A1DATA[7:0]}),
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.DOPA({A1DATA[17], A1DATA[8]}),
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.ADDRA(A1ADDR),
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.CLKA(CLK2 ^ !CLKPOL2),
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.ENA(A1EN),
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.SSRA(|0),
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.WEA(2'b00),
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.DIB({B1DATA[16:9], B1DATA[7:0]}),
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.DIPB({B1DATA[17], B1DATA[8]}),
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.DOB(DOB),
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.DOPB(DOPB),
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.ADDRB(B1ADDR),
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.CLKB(CLK3 ^ !CLKPOL3),
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.ENB(|1),
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.SSRB(|0),
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.WEB(B1EN)
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);
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end else if (CFG_DBITS == 36) begin
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wire [31:0] DOB;
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wire [3:0] DOPB;
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RAMB16BWE_S36_S36 #(
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`include "brams_init_18.vh"
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.WRITE_MODE_A("READ_FIRST"),
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.WRITE_MODE_B("READ_FIRST"),
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) _TECHMAP_REPLACE_ (
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.DIA(32'd0),
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.DIPA(4'd0),
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.DOA({A1DATA[34:27], A1DATA[25:18], A1DATA[16:9], A1DATA[7:0]}),
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.DOPA({A1DATA[35], A1DATA[26], A1DATA[17], A1DATA[8]}),
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.ADDRA(A1ADDR),
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.CLKA(CLK2 ^ !CLKPOL2),
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.ENA(A1EN),
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.SSRA(|0),
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.WEA(4'b0000),
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.DIB({B1DATA[34:27], B1DATA[25:18], B1DATA[16:9], B1DATA[7:0]}),
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.DIPB({B1DATA[35], B1DATA[26], B1DATA[17], B1DATA[8]}),
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.DOB(DOB),
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.DOPB(DOPB),
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.ADDRB(B1ADDR),
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.CLKB(CLK3 ^ !CLKPOL3),
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.ENB(|1),
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.SSRB(|0),
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.WEB(B1EN)
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);
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end else begin
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$error("Strange block RAM data width.");
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end endgenerate
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endmodule
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