mirror of https://github.com/YosysHQ/yosys.git
211 lines
7.4 KiB
Verilog
211 lines
7.4 KiB
Verilog
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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* 2019 Eddie Hung <eddie@fpgeh.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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// ============================================================================
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// Box containing MUXF7.[AB] + MUXF8,
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// Necessary to make these an atomic unit so that
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// ABC cannot optimise just one of the MUXF7 away
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// and expect to save on its delay
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(* abc9_box, lib_whitebox *)
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module \$__XILINX_MUXF78 (output O, input I0, I1, I2, I3, S0, S1);
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assign O = S1 ? (S0 ? I3 : I2)
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: (S0 ? I1 : I0);
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specify
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(I0 => O) = 294;
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(I1 => O) = 297;
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(I2 => O) = 311;
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(I3 => O) = 317;
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(S0 => O) = 390;
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(S1 => O) = 273;
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endspecify
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endmodule
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// Box to emulate async behaviour of FDC*
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(* abc9_box, lib_whitebox *)
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module \$__ABC9_ASYNC0 (input A, S, output Y);
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assign Y = S ? 1'b0 : A;
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specify
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(A => Y) = 0;
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// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L270
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(S => Y) = 764;
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endspecify
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endmodule
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// Box to emulate async behaviour of FDP*
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(* abc9_box, lib_whitebox *)
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module \$__ABC9_ASYNC1 (input A, S, output Y);
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assign Y = S ? 1'b1 : A;
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specify
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(A => Y) = 0;
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// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L270
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(S => Y) = 764;
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endspecify
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endmodule
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// Box to emulate comb/seq behaviour of RAM{32,64} and SRL{16,32}
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// Necessary since RAMD* and SRL* have both combinatorial (i.e.
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// same-cycle read operation) and sequential (write operation
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// is only committed on the next clock edge).
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// To model the combinatorial path, such cells have to be split
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// into comb and seq parts, with this box modelling only the former.
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(* abc9_box *)
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module \$__ABC9_RAM6 (input A, input [5:0] S, output Y);
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specify
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(A => Y) = 0;
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(S[0] => Y) = 642;
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(S[1] => Y) = 631;
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(S[2] => Y) = 472;
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(S[3] => Y) = 407;
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(S[4] => Y) = 238;
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(S[5] => Y) = 127;
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endspecify
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endmodule
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// Box to emulate comb/seq behaviour of RAM128
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(* abc9_box *)
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module \$__ABC9_RAM7 (input A, input [6:0] S, output Y);
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specify
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(A => Y) = 0;
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// https://github.com/SymbiFlow/prjxray-db/blob/1c85daf1b115da4d27ca83c6b89f53a94de39748/artix7/timings/slicel.sdf#L867
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(S[0] => Y) = 642 + 223 /* to cross F7BMUX */ + 174 /* CMUX */;
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(S[1] => Y) = 631 + 223 /* to cross F7BMUX */ + 174 /* CMUX */;
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(S[2] => Y) = 472 + 223 /* to cross F7BMUX */ + 174 /* CMUX */;
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(S[3] => Y) = 407 + 223 /* to cross F7BMUX */ + 174 /* CMUX */;
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(S[4] => Y) = 238 + 223 /* to cross F7BMUX */ + 174 /* CMUX */;
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(S[5] => Y) = 127 + 223 /* to cross F7BMUX */ + 174 /* CMUX */;
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(S[6] => Y) = 0 + 296 /* to select F7BMUX */ + 174 /* CMUX */;
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endspecify
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endmodule
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// Boxes used to represent the comb behaviour of DSP48E1
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(* abc9_box *)
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module $__ABC9_DSP48E1 (
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input [29:0] $A,
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input [17:0] $B,
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input [47:0] $C,
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input [24:0] $D,
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input [47:0] $P,
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input [47:0] $PCIN,
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input [47:0] $PCOUT,
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output [47:0] P,
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output [47:0] PCOUT
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);
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parameter integer ADREG = 1;
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parameter integer AREG = 1;
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parameter integer BREG = 1;
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parameter integer CREG = 1;
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parameter integer DREG = 1;
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parameter integer MREG = 1;
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parameter integer PREG = 1;
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parameter USE_DPORT = "FALSE";
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parameter USE_MULT = "MULTIPLY";
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function integer \A.P.comb ;
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begin
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if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") \A.P.comb = 2823;
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else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") \A.P.comb = 3806;
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else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") \A.P.comb = 1523;
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end
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endfunction
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function integer \A.PCOUT.comb ;
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begin
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if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") \A.PCOUT.comb = 2970;
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else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") \A.PCOUT.comb = 3954;
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else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") \A.PCOUT.comb = 1671;
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end
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endfunction
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function integer \B.P.comb ;
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begin
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if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") \B.P.comb = 2690;
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else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") \B.P.comb = 2690;
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else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") \B.P.comb = 1509;
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end
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endfunction
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function integer \B.PCOUT.comb ;
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begin
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if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") \B.PCOUT.comb = 2838;
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else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") \B.PCOUT.comb = 2838;
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else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") \B.PCOUT.comb = 1658;
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end
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endfunction
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function integer \C.P.comb ;
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begin
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if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") \C.P.comb = 1325;
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else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") \C.P.comb = 1325;
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else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") \C.P.comb = 1325;
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end
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endfunction
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function integer \C.PCOUT.comb ;
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begin
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if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") \C.PCOUT.comb = 1474;
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else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") \C.PCOUT.comb = 1474;
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else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") \C.PCOUT.comb = 1474;
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end
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endfunction
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function integer \D.P.comb ;
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begin
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if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") \D.P.comb = 3717;
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end
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endfunction
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function integer \D.PCOUT.comb ;
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begin
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if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") \D.PCOUT.comb = 3700;
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end
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endfunction
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specify
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($P *> P) = 0;
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($PCOUT *> PCOUT) = 0;
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endspecify
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// Identical comb delays to DSP48E1 in cells_sim.v
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generate
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if (PREG == 0 && MREG == 0 && AREG == 0 && ADREG == 0)
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specify
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($A *> P) = \A.P.comb ();
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($A *> PCOUT) = \A.PCOUT.comb ();
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endspecify
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if (PREG == 0 && MREG == 0 && BREG == 0)
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specify
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($B *> P) = \B.P.comb ();
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($B *> PCOUT) = \B.PCOUT.comb ();
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endspecify
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if (PREG == 0 && CREG == 0)
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specify
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($C *> P) = \C.P.comb ();
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($C *> PCOUT) = \C.PCOUT.comb ();
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endspecify
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if (PREG == 0 && MREG == 0 && ADREG == 0 && DREG == 0)
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specify
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($D *> P) = \D.P.comb ();
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($D *> PCOUT) = \D.PCOUT.comb ();
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endspecify
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if (PREG == 0)
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specify
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($PCIN *> P) = 1107;
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($PCIN *> PCOUT) = 1255;
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endspecify
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endgenerate
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endmodule
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