mirror of https://github.com/YosysHQ/yosys.git
144 lines
5.6 KiB
Verilog
144 lines
5.6 KiB
Verilog
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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* 2019 Eddie Hung <eddie@fpgeh.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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// ============================================================================
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module FDRE (output reg Q, input C, CE, D, R);
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parameter [0:0] INIT = 1'b0;
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parameter [0:0] IS_C_INVERTED = 1'b0;
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parameter [0:0] IS_D_INVERTED = 1'b0;
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parameter [0:0] IS_CLR_INVERTED = 1'b0;
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wire \$nextQ ;
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\$__ABC_FDRE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .R(R));
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\$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q));
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endmodule
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module FDRE_1 (output reg Q, input C, CE, D, R);
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parameter [0:0] INIT = 1'b0;
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wire \$nextQ ;
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\$__ABC_FDRE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .R(R));
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\$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q));
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endmodule
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module FDCE (output reg Q, input C, CE, D, CLR);
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parameter [0:0] INIT = 1'b0;
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parameter [0:0] IS_C_INVERTED = 1'b0;
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parameter [0:0] IS_D_INVERTED = 1'b0;
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parameter [0:0] IS_CLR_INVERTED = 1'b0;
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wire \$nextQ , \$currQ ;
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\$__ABC_FDCE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .CLR(CLR));
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\$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q));
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\$__ABC_MUX_ abc_async_mux (.A(\$currQ ), .B(1'b0), .S(CLR), .Y(Q));
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endmodule
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module FDCE_1 (output reg Q, input C, CE, D, CLR);
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parameter [0:0] INIT = 1'b0;
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wire \$nextQ , \$currQ ;
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\$__ABC_FDCE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .CLR(CLR));
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\$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ ));
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\$__ABC_MUX_ abc_async_mux (.A(\$currQ ), .B(1'b0), .S(CLR), .Y(Q));
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endmodule
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module FDPE (output reg Q, input C, CE, D, PRE);
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parameter [0:0] INIT = 1'b0;
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parameter [0:0] IS_C_INVERTED = 1'b0;
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parameter [0:0] IS_D_INVERTED = 1'b0;
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parameter [0:0] IS_PRE_INVERTED = 1'b0;
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wire \$nextQ , \$currQ ;
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\$__ABC_FDCE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .PRE(PRE));
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\$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q));
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generate
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if (IS_PRE_INVERTED)
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\$__ABC_MUX_ abc_async_mux (.A(\$currQ ), .B(1'b1), .S(PRE), .Y(Q));
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else
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\$__ABC_MUX_ abc_async_mux (.A(1'b1), .B(\$currQ ), .S(PRE), .Y(Q));
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endgenerate
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endmodule
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module FDPE_1 (output reg Q, input C, CE, D, CLR);
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parameter [0:0] INIT = 1'b0;
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wire \$nextQ , \$currQ ;
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\$__ABC_FDCE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .PRE(PRE));
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\$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q));
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\$__ABC_MUX_ abc_async_mux (.A(\$currQ ), .B(1'b1), .S(PRE), .Y(Q));
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endmodule
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`ifndef _ABC
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module \$__ABC_FF_ (input C, D, output Q);
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endmodule
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(* abc_box_id = 1000 *)
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module \$__ABC_FD_ASYNC_MUX_ (input A, B, S, output Q);
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// assign Q = S ? B : A;
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endmodule
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(* abc_box_id = 1001, lib_whitebox, abc_flop = "FDRE,D,Q,\\$pastQ" *)
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module \$__ABC_FDRE (output Q, input C, CE, D, R, \$pastQ );
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parameter [0:0] INIT = 1'b0;
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//parameter [0:0] IS_C_INVERTED = 1'b0;
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parameter [0:0] IS_D_INVERTED = 1'b0;
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parameter [0:0] IS_R_INVERTED = 1'b0;
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assign Q = (R ^ IS_R_INVERTED) ? 1'b0 : (CE ? (D ^ IS_D_INVERTED) : \$pastQ );
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endmodule
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(* abc_box_id = 1002, lib_whitebox, abc_flop = "FDRE_1,D,Q,\\$pastQ" *)
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module \$__ABC_FDRE_1 (output Q, input C, CE, D, R, \$pastQ );
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parameter [0:0] INIT = 1'b0;
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//parameter [0:0] IS_C_INVERTED = 1'b0;
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parameter [0:0] IS_D_INVERTED = 1'b0;
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parameter [0:0] IS_R_INVERTED = 1'b0;
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assign Q = (R ^ IS_R_INVERTED) ? 1'b0 : (CE ? (D ^ IS_D_INVERTED) : \$pastQ );
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endmodule
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(* abc_box_id = 1003, lib_whitebox, abc_flop = "FDCE,D,Q,\\$pastQ" *)
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module \$__ABC_FDCE (output Q, input C, CE, D, CLR, \$pastQ );
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parameter [0:0] INIT = 1'b0;
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//parameter [0:0] IS_C_INVERTED = 1'b0;
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parameter [0:0] IS_D_INVERTED = 1'b0;
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//parameter [0:0] IS_CLR_INVERTED = 1'b0;
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assign Q = CE ? (D ^ IS_D_INVERTED) : \$pastQ ;
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endmodule
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(* abc_box_id = 1004, lib_whitebox, abc_flop = "FDCE_1,D,Q,\\$pastQ" *)
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module \$__ABC_FDCE_1 (output Q, input C, CE, D, CLR, \$pastQ );
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parameter [0:0] INIT = 1'b0;
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//parameter [0:0] IS_C_INVERTED = 1'b0;
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parameter [0:0] IS_D_INVERTED = 1'b0;
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//parameter [0:0] IS_CLR_INVERTED = 1'b0;
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assign Q = CE ? (D ^ IS_D_INVERTED) : \$pastQ ;
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endmodule
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(* abc_box_id = 1005, lib_whitebox, abc_flop = "FDPE,D,Q,\\$pastQ" *)
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module \$__ABC_FDPE (output Q, input C, CE, D, PRE, \$pastQ );
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parameter [0:0] INIT = 1'b0;
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//parameter [0:0] IS_C_INVERTED = 1'b0;
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parameter [0:0] IS_D_INVERTED = 1'b0;
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//parameter [0:0] IS_PRE_INVERTED = 1'b0;
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assign Q = CE ? (D ^ IS_D_INVERTED) : \$pastQ ;
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endmodule
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(* abc_box_id = 1006, lib_whitebox, abc_flop = "FDPE_1,D,Q,\\$pastQ" *)
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module \$__ABC_FDPE_1 (output Q, input C, CE, D, PRE, \$pastQ );
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parameter [0:0] INIT = 1'b0;
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//parameter [0:0] IS_C_INVERTED = 1'b0;
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parameter [0:0] IS_D_INVERTED = 1'b0;
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//parameter [0:0] IS_PRE_INVERTED = 1'b0;
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assign Q = CE ? (D ^ IS_D_INVERTED) : \$pastQ ;
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endmodule
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`endif
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