mirror of https://github.com/YosysHQ/yosys.git
375 lines
11 KiB
C++
375 lines
11 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/register.h"
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#include "kernel/rtlil.h"
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#include "kernel/log.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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static void rename_in_module(RTLIL::Module *module, std::string from_name, std::string to_name, bool flag_output)
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{
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from_name = RTLIL::escape_id(from_name);
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to_name = RTLIL::escape_id(to_name);
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if (module->count_id(to_name))
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log_cmd_error("There is already an object `%s' in module `%s'.\n", to_name.c_str(), module->name.c_str());
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for (auto &it : module->wires_)
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if (it.first == from_name) {
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Wire *w = it.second;
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log("Renaming wire %s to %s in module %s.\n", log_id(w), log_id(to_name), log_id(module));
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module->rename(w, to_name);
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if (w->port_id || flag_output) {
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if (flag_output)
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w->port_output = true;
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module->fixup_ports();
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}
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return;
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}
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for (auto &it : module->cells_)
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if (it.first == from_name) {
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if (flag_output)
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log_cmd_error("Called with -output but the specified object is a cell.\n");
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log("Renaming cell %s to %s in module %s.\n", log_id(it.second), log_id(to_name), log_id(module));
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module->rename(it.second, to_name);
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return;
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}
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log_cmd_error("Object `%s' not found!\n", from_name.c_str());
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}
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static std::string derive_name_from_src(const std::string &src, int counter)
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{
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std::string src_base = src.substr(0, src.find('|'));
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if (src_base.empty())
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return stringf("$%d", counter);
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else
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return stringf("\\%s$%d", src_base.c_str(), counter);
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}
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static IdString derive_name_from_wire(const RTLIL::Cell &cell)
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{
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// Find output
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const SigSpec *output = nullptr;
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int num_outputs = 0;
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for (auto &connection : cell.connections()) {
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if (cell.output(connection.first)) {
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output = &connection.second;
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num_outputs++;
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}
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}
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if (num_outputs != 1) // Skip cells thad drive multiple outputs
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return cell.name;
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std::string name = "";
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for (auto &chunk : output->chunks()) {
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// Skip cells that drive privately named wires
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if (!chunk.wire || chunk.wire->name.str()[0] == '$')
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return cell.name;
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if (name != "")
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name += "$";
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name += chunk.wire->name.str();
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if (chunk.wire->width != chunk.width) {
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name += "[";
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if (chunk.width != 1)
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name += std::to_string(chunk.offset + chunk.width) + ":";
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name += std::to_string(chunk.offset) + "]";
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}
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}
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return name + cell.type.str();
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}
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struct RenamePass : public Pass {
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RenamePass() : Pass("rename", "rename object in the design") { }
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void help() YS_OVERRIDE
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" rename old_name new_name\n");
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log("\n");
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log("Rename the specified object. Note that selection patterns are not supported\n");
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log("by this command.\n");
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log("\n");
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log("\n");
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log("\n");
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log(" rename -output old_name new_name\n");
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log("\n");
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log("Like above, but also make the wire an output. This will fail if the object is\n");
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log("not a wire.\n");
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log("\n");
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log("\n");
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log(" rename -src [selection]\n");
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log("\n");
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log("Assign names auto-generated from the src attribute to all selected wires and\n");
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log("cells with private names.\n");
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log("\n");
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log("\n");
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log(" rename -wire [selection]\n");
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log("\n");
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log("Assign auto-generated names based on the wires they drive to all selected\n");
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log("cells with private names. Ignores cells driving privatly named wires.\n");
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log("\n");
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log("\n");
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log(" rename -enumerate [-pattern <pattern>] [selection]\n");
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log("\n");
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log("Assign short auto-generated names to all selected wires and cells with private\n");
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log("names. The -pattern option can be used to set the pattern for the new names.\n");
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log("The character %% in the pattern is replaced with a integer number. The default\n");
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log("pattern is '_%%_'.\n");
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log("\n");
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log("\n");
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log(" rename -hide [selection]\n");
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log("\n");
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log("Assign private names (the ones with $-prefix) to all selected wires and cells\n");
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log("with public names. This ignores all selected ports.\n");
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log("\n");
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log("\n");
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log(" rename -top new_name\n");
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log("\n");
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log("Rename top module.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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{
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std::string pattern_prefix = "_", pattern_suffix = "_";
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bool flag_src = false;
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bool flag_wire = false;
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bool flag_enumerate = false;
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bool flag_hide = false;
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bool flag_top = false;
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bool flag_output = false;
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bool got_mode = false;
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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std::string arg = args[argidx];
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if (arg == "-src" && !got_mode) {
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flag_src = true;
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got_mode = true;
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continue;
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}
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if (arg == "-output" && !got_mode) {
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flag_output = true;
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got_mode = true;
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continue;
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}
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if (arg == "-wire" && !got_mode) {
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flag_wire = true;
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got_mode = true;
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continue;
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}
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if (arg == "-enumerate" && !got_mode) {
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flag_enumerate = true;
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got_mode = true;
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continue;
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}
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if (arg == "-hide" && !got_mode) {
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flag_hide = true;
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got_mode = true;
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continue;
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}
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if (arg == "-top" && !got_mode) {
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flag_top = true;
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got_mode = true;
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continue;
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}
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if (arg == "-pattern" && argidx+1 < args.size() && args[argidx+1].find('%') != std::string::npos) {
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int pos = args[++argidx].find('%');
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pattern_prefix = args[argidx].substr(0, pos);
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pattern_suffix = args[argidx].substr(pos+1);
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continue;
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}
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break;
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}
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if (flag_src)
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{
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extra_args(args, argidx, design);
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for (auto &mod : design->modules_)
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{
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int counter = 0;
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RTLIL::Module *module = mod.second;
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if (!design->selected(module))
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continue;
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dict<RTLIL::IdString, RTLIL::Wire*> new_wires;
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for (auto &it : module->wires_) {
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if (it.first[0] == '$' && design->selected(module, it.second))
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it.second->name = derive_name_from_src(it.second->get_src_attribute(), counter++);
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new_wires[it.second->name] = it.second;
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}
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module->wires_.swap(new_wires);
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module->fixup_ports();
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dict<RTLIL::IdString, RTLIL::Cell*> new_cells;
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for (auto &it : module->cells_) {
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if (it.first[0] == '$' && design->selected(module, it.second))
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it.second->name = derive_name_from_src(it.second->get_src_attribute(), counter++);
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new_cells[it.second->name] = it.second;
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}
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module->cells_.swap(new_cells);
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}
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}
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else
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if (flag_wire)
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{
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extra_args(args, argidx, design);
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for (auto &mod : design->modules_)
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{
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RTLIL::Module *module = mod.second;
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if (!design->selected(module))
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continue;
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dict<RTLIL::IdString, RTLIL::Cell*> new_cells;
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for (auto &it : module->cells_) {
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if (it.first[0] == '$' && design->selected(module, it.second))
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it.second->name = derive_name_from_wire(*it.second);
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new_cells[it.second->name] = it.second;
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}
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module->cells_.swap(new_cells);
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}
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}
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else
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if (flag_enumerate)
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{
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extra_args(args, argidx, design);
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for (auto &mod : design->modules_)
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{
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int counter = 0;
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RTLIL::Module *module = mod.second;
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if (!design->selected(module))
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continue;
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dict<RTLIL::IdString, RTLIL::Wire*> new_wires;
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for (auto &it : module->wires_) {
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if (it.first[0] == '$' && design->selected(module, it.second))
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do it.second->name = stringf("\\%s%d%s", pattern_prefix.c_str(), counter++, pattern_suffix.c_str());
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while (module->count_id(it.second->name) > 0);
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new_wires[it.second->name] = it.second;
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}
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module->wires_.swap(new_wires);
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module->fixup_ports();
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dict<RTLIL::IdString, RTLIL::Cell*> new_cells;
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for (auto &it : module->cells_) {
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if (it.first[0] == '$' && design->selected(module, it.second))
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do it.second->name = stringf("\\%s%d%s", pattern_prefix.c_str(), counter++, pattern_suffix.c_str());
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while (module->count_id(it.second->name) > 0);
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new_cells[it.second->name] = it.second;
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}
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module->cells_.swap(new_cells);
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}
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}
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else
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if (flag_hide)
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{
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extra_args(args, argidx, design);
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for (auto &mod : design->modules_)
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{
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RTLIL::Module *module = mod.second;
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if (!design->selected(module))
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continue;
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dict<RTLIL::IdString, RTLIL::Wire*> new_wires;
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for (auto &it : module->wires_) {
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if (design->selected(module, it.second))
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if (it.first[0] == '\\' && it.second->port_id == 0)
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it.second->name = NEW_ID;
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new_wires[it.second->name] = it.second;
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}
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module->wires_.swap(new_wires);
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module->fixup_ports();
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dict<RTLIL::IdString, RTLIL::Cell*> new_cells;
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for (auto &it : module->cells_) {
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if (design->selected(module, it.second))
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if (it.first[0] == '\\')
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it.second->name = NEW_ID;
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new_cells[it.second->name] = it.second;
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}
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module->cells_.swap(new_cells);
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}
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}
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else
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if (flag_top)
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{
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if (argidx+1 != args.size())
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log_cmd_error("Invalid number of arguments!\n");
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IdString new_name = RTLIL::escape_id(args[argidx]);
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RTLIL::Module *module = design->top_module();
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if (module == NULL)
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log_cmd_error("No top module found!\n");
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log("Renaming module %s to %s.\n", log_id(module), log_id(new_name));
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design->rename(module, new_name);
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}
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else
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{
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if (argidx+2 != args.size())
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log_cmd_error("Invalid number of arguments!\n");
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std::string from_name = args[argidx++];
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std::string to_name = args[argidx++];
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if (!design->selected_active_module.empty())
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{
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if (design->modules_.count(design->selected_active_module) > 0)
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rename_in_module(design->modules_.at(design->selected_active_module), from_name, to_name, flag_output);
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}
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else
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{
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if (flag_output)
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log_cmd_error("Mode -output requires that there is an active module selected.\n");
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for (auto &mod : design->modules_) {
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if (mod.first == from_name || RTLIL::unescape_id(mod.first) == from_name) {
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to_name = RTLIL::escape_id(to_name);
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log("Renaming module %s to %s.\n", mod.first.c_str(), to_name.c_str());
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RTLIL::Module *module = mod.second;
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design->modules_.erase(module->name);
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module->name = to_name;
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design->modules_[module->name] = module;
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goto rename_ok;
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}
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}
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log_cmd_error("Object `%s' not found!\n", from_name.c_str());
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rename_ok:;
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}
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}
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}
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} RenamePass;
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PRIVATE_NAMESPACE_END
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