yosys/passes/proc
Clifford Wolf c094c53de8 Removed RTLIL::SigSpec::optimize() 2014-07-23 20:32:28 +02:00
..
Makefile.inc Major improvements in mem2reg and added "init" sync rules 2013-11-21 13:49:00 +01:00
proc.cc Major improvements in mem2reg and added "init" sync rules 2013-11-21 13:49:00 +01:00
proc_arst.cc Fixed all users of SigSpec::chunks_rw() and removed it 2014-07-23 15:36:09 +02:00
proc_clean.cc SigSpec refactoring: using the accessor functions everywhere 2014-07-22 20:39:37 +02:00
proc_dff.cc Removed RTLIL::SigSpec::optimize() 2014-07-23 20:32:28 +02:00
proc_init.cc Removed RTLIL::SigSpec::optimize() 2014-07-23 20:32:28 +02:00
proc_mux.cc Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3 2014-07-23 09:52:55 +02:00
proc_rmdead.cc Added help messages to proc_* passes 2013-03-01 09:26:29 +01:00