.gitignore
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ecp5: First BRAM type maps successfully
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2018-10-10 16:35:19 +01:00 |
abc_5g.box
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Fix DO4 typo
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2019-06-28 09:45:40 -07:00 |
abc_5g.lut
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ecp5: Add abc9 option
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2019-06-14 17:15:02 +01:00 |
bram.txt
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ecp5: First BRAM type maps successfully
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2018-10-10 16:35:19 +01:00 |
brams_connect.py
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ecp5: Script for BRAM IO connections
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2018-10-10 16:11:00 +01:00 |
brams_init.py
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ecp5: First BRAM type maps successfully
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2018-10-10 16:35:19 +01:00 |
brams_map.v
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ecp5: Disable LSR inversion
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2018-10-16 12:48:39 +01:00 |
cells_bb.v
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ecp5: Add DDRDLLA
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2019-02-19 19:34:37 +00:00 |
cells_map.v
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Merge origin/master
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2019-06-27 11:20:15 -07:00 |
dsp_map.v
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OUT port to Y in generic DSP
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2019-07-15 14:45:47 -07:00 |
latches_map.v
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ecp5: Add latch inference
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2018-10-19 15:16:40 +01:00 |
lutram.txt
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synth_ecp5: rename dram to lutram everywhere.
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2019-07-16 20:45:12 +00:00 |