mirror of https://github.com/YosysHQ/yosys.git
83 lines
1.5 KiB
Verilog
83 lines
1.5 KiB
Verilog
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module task_func_test01(clk, a, b, c, x, y, z, w);
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input clk;
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input [7:0] a, b, c;
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output reg [7:0] x, y, z, w;
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function [7:0] sum_shift;
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input [3:0] s1, s2, s3;
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sum_shift = s1 + (s2 << 2) + (s3 << 4);
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endfunction
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task reset_w;
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w = 0;
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endtask
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task add_to;
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output [7:0] out;
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input [7:0] in;
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out = out + in;
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endtask
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always @(posedge clk) begin
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x = sum_shift(a, b, c);
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y = sum_shift(a[7:4], b[5:2], c[3:0]);
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z = sum_shift(a[0], b[5:4], c >> 5) ^ sum_shift(1, 2, 3);
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reset_w;
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add_to(w, x);
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add_to(w, y);
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add_to(w, z);
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end
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endmodule
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// -------------------------------------------------------------------
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module task_func_test02(clk, a, b, c, x, y, z, w);
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input clk;
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input [7:0] a, b, c;
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output reg [7:0] x, y, z, w;
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function [7:0] sum_shift(input [3:0] s1, s2, s3);
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sum_shift = s1 + (s2 << 2) + (s3 << 4);
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endfunction
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task reset_w;
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w = 0;
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endtask
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task add_to(output [7:0] out, input [7:0] in);
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out = out + in;
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endtask
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always @(posedge clk) begin
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x = sum_shift(a, b, c);
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y = sum_shift(a[7:4], b[5:2], c[3:0]);
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z = sum_shift(a[0], b[5:4], c >> 5) ^ sum_shift(1, 2, 3);
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reset_w;
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add_to(w, x);
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add_to(w, y);
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add_to(w, z);
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end
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endmodule
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// -------------------------------------------------------------------
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module task_func_test03( input [7:0] din_a, input [7:0] din_b, output [7:0] dout_a);
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assign dout_a = test(din_a,din_b);
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function [7:0] test;
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input [7:0] a;
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input [7:0] b;
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begin : TEST
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integer i;
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for (i = 0; i <= 7; i = i + 1)
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test[i] = a[i] & b[i];
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end
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endfunction
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endmodule
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