mirror of https://github.com/YosysHQ/yosys.git
228 lines
6.8 KiB
TeX
228 lines
6.8 KiB
TeX
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\section{Yosys by example -- Beyond Synthesis}
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\begin{frame}
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\sectionpage
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\end{frame}
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\begin{frame}{Overview}
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This section contains 2 subsections:
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\begin{itemize}
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\item Interactive Design Investigation
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\item Symbolic Model Checking
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\end{itemize}
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\end{frame}
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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\subsection{Interactive Design Investigation}
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\begin{frame}
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\subsectionpage
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\subsectionpagesuffix
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\end{frame}
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\begin{frame}{\subsecname}
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Yosys can also be used to investigate designs (or netlists created
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from other tools).
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\begin{itemize}
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\item
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The selection mechanism (see slides ``Using Selections''), especially patterns such
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as {\tt \%ci} and {\tt \%co}, can be used to figure out how parts of the design
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are connected.
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\item
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Commands such as {\tt submod}, {\tt expose}, {\tt splice}, \dots can be used
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to transform the design into an equivalent design that is easier to analyse.
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\item
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Commands such as {\tt eval} and {\tt sat} can be used to investigate the
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behavior of the circuit.
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\end{itemize}
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\end{frame}
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\begin{frame}[t, fragile]{Example: Reorganizing a module}
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\begin{columns}
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\column[t]{4cm}
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\lstinputlisting[basicstyle=\ttfamily\fontsize{6pt}{7pt}\selectfont, language=verilog]{PRESENTATION_ExOth/scrambler.v}
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\column[t]{7cm}
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\begin{lstlisting}[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys, frame=single]
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read_verilog scrambler.v
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hierarchy; proc;;
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cd scrambler
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submod -name xorshift32 \
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xs %c %ci %D %c %ci:+[D] %D \
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%ci*:-$dff xs %co %ci %d
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\end{lstlisting}
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\end{columns}
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\hfil\includegraphics[width=11cm,trim=0 0cm 0 1.5cm]{PRESENTATION_ExOth/scrambler_p01.pdf}
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\hfil\includegraphics[width=11cm,trim=0 0cm 0 2cm]{PRESENTATION_ExOth/scrambler_p02.pdf}
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\end{frame}
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\begin{frame}[t, fragile]{Example: Analysis of circuit behavior}
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\begin{lstlisting}[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
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> read_verilog scrambler.v
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> hierarchy; proc;; cd scrambler
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> submod -name xorshift32 xs %c %ci %D %c %ci:+[D] %D %ci*:-$dff xs %co %ci %d
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> cd xorshift32
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> rename n2 in
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> rename n1 out
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> eval -set in 1 -show out
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Eval result: \out = 270369.
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> eval -set in 270369 -show out
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Eval result: \out = 67634689.
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> sat -set out 632435482
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Signal Name Dec Hex Bin
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-------------------- ---------- ---------- -------------------------------------
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\in 745495504 2c6f5bd0 00101100011011110101101111010000
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\out 632435482 25b2331a 00100101101100100011001100011010
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\end{lstlisting}
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\end{frame}
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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\subsection{Symbolic Model Checking}
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\begin{frame}
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\subsectionpage
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\subsectionpagesuffix
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\end{frame}
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\begin{frame}{\subsecname}
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Symbolic Model Checking (SMC) is used to formally prove that a circuit has
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(or has not) a given property.
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\bigskip
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One application is Formal Equivalence Checking: Proving that two circuits
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are identical. For example this is a very useful feature when debugging custom
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passes in Yosys.
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\bigskip
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Other applications include checking if a module conforms to interface
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standards.
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\bigskip
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The {\tt sat} command in Yosys can be used to perform Symbolic Model Checking.
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\end{frame}
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\begin{frame}[t]{Example: Formal Equivalence Checking (1/2)}
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Remember the following example?
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\vskip1em
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\vbox to 0cm{
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\vskip-0.3cm
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\lstinputlisting[basicstyle=\ttfamily\fontsize{6pt}{7pt}\selectfont, language=verilog]{PRESENTATION_ExSyn/techmap_01_map.v}
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}\vbox to 0cm{
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\vskip-0.5cm
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\lstinputlisting[xleftmargin=5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single, language=verilog]{PRESENTATION_ExSyn/techmap_01.v}
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\lstinputlisting[xleftmargin=5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys, frame=single]{PRESENTATION_ExSyn/techmap_01.ys}}
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\vskip5cm\hskip5cm
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Lets see if it is correct..
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\end{frame}
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\begin{frame}[t, fragile]{Example: Formal Equivalence Checking (2/2)}
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\begin{lstlisting}[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys, frame=single]
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# read test design
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read_verilog techmap_01.v
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hierarchy -top test
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# create two version of the design: test_orig and test_mapped
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copy test test_orig
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rename test test_mapped
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# apply the techmap only to test_mapped
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techmap -map techmap_01_map.v test_mapped
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# create a miter circuit to test equivalence
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miter -equiv -make_assert -make_outputs test_orig test_mapped miter
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flatten miter
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# run equivalence check
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sat -verify -prove-asserts -show-inputs -show-outputs miter
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\end{lstlisting}
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\dots
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\begin{lstlisting}[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont]
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Solving problem with 945 variables and 2505 clauses..
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SAT proof finished - no model found: SUCCESS!
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\end{lstlisting}
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\end{frame}
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\begin{frame}[t, fragile]{Example: Symbolic Model Checking (1/2)}
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\small
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The following AXI4 Stream Master has a bug. But the bug is not exposed if the
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slave keeps {\tt tready} asserted all the time. (Something a test bench might do.)
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\medskip
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Symbolic Model Checking can be used to expose the bug and find a sequence
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of values for {\tt tready} that yield the incorrect behavior.
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\vskip-1em
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\begin{columns}
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\column[t]{5cm}
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\lstinputlisting[basicstyle=\ttfamily\fontsize{5pt}{6pt}\selectfont, language=verilog]{PRESENTATION_ExOth/axis_master.v}
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\column[t]{5cm}
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\lstinputlisting[basicstyle=\ttfamily\fontsize{5pt}{6pt}\selectfont, language=verilog]{PRESENTATION_ExOth/axis_test.v}
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\end{columns}
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\end{frame}
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\begin{frame}[t, fragile]{Example: Symbolic Model Checking (2/2)}
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\begin{lstlisting}[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys, frame=single]
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read_verilog -sv axis_master.v axis_test.v
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hierarchy -top axis_test
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proc; flatten;;
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sat -seq 50 -prove-asserts
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\end{lstlisting}
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\bigskip
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\dots with unmodified {\tt axis\_master.v}:
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\begin{lstlisting}[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont]
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Solving problem with 159344 variables and 442126 clauses..
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SAT proof finished - model found: FAIL!
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\end{lstlisting}
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\bigskip
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\dots with fixed {\tt axis\_master.v}:
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\begin{lstlisting}[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont]
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Solving problem with 159144 variables and 441626 clauses..
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SAT proof finished - no model found: SUCCESS!
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\end{lstlisting}
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\end{frame}
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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\subsection{Summary}
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\begin{frame}{\subsecname}
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\begin{itemize}
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\item Yosys provides useful features beyond synthesis.
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\item The commands {\tt sat} and {\tt eval} can be used to analyse the behavior of a circuit.
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\item The {\tt sat} command can also be used for symbolic model checking.
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\item This can be useful for debugging and testing designs and Yosys extensions alike.
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\end{itemize}
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\bigskip
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\bigskip
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\begin{center}
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Questions?
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\end{center}
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\bigskip
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\bigskip
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\begin{center}
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\url{http://www.clifford.at/yosys/}
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\end{center}
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\end{frame}
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