mirror of https://github.com/YosysHQ/yosys.git
81 lines
2.8 KiB
Verilog
81 lines
2.8 KiB
Verilog
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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* 2019 Eddie Hung <eddie@fpgeh.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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// ============================================================================
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// Box containing MUXF7.[AB] + MUXF8,
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// Necessary to make these an atomic unit so that
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// ABC cannot optimise just one of the MUXF7 away
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// and expect to save on its delay
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(* abc9_box_id = 3, lib_whitebox *)
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module \$__XILINX_MUXF78 (output O, input I0, I1, I2, I3, S0, S1);
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assign O = S1 ? (S0 ? I3 : I2)
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: (S0 ? I1 : I0);
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endmodule
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module \$__ABC9_FF_ (input D, output Q);
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endmodule
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// Box to emulate async behaviour of FDC*
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(* abc9_box_id = 1000, lib_whitebox *)
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module \$__ABC9_ASYNC0 (input A, S, output Y);
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assign Y = S ? 1'b0 : A;
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endmodule
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// Box to emulate async behaviour of FDP*
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(* abc9_box_id = 1001, lib_whitebox *)
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module \$__ABC9_ASYNC1 (input A, S, output Y);
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assign Y = S ? 1'b1 : A;
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endmodule
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// Box to emulate comb/seq behaviour of RAM{32,64} and SRL{16,32}
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// Necessary since RAMD* and SRL* have both combinatorial (i.e.
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// same-cycle read operation) and sequential (write operation
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// is only committed on the next clock edge).
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// To model the combinatorial path, such cells have to be split
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// into comb and seq parts, with this box modelling only the former.
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(* abc9_box_id=2000 *)
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module \$__ABC9_LUT6 (input A, input [5:0] S, output Y);
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endmodule
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// Box to emulate comb/seq behaviour of RAM128
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(* abc9_box_id=2001 *)
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module \$__ABC9_LUT7 (input A, input [6:0] S, output Y);
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endmodule
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// Boxes used to represent the comb behaviour of various modes
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// of DSP48E1
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`define ABC9_DSP48E1(__NAME__) """
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module __NAME__ (
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input [29:0] $A,
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input [17:0] $B,
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input [47:0] $C,
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input [24:0] $D,
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input [47:0] $P,
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input [47:0] $PCIN,
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input [47:0] $PCOUT,
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output [47:0] P,
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output [47:0] PCOUT);
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endmodule
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"""
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(* abc9_box_id=3000 *) `ABC9_DSP48E1($__ABC9_DSP48E1_MULT)
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(* abc9_box_id=3001 *) `ABC9_DSP48E1($__ABC9_DSP48E1_MULT_DPORT)
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(* abc9_box_id=3002 *) `ABC9_DSP48E1($__ABC9_DSP48E1)
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`undef ABC9_DSP48E1
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