mirror of https://github.com/YosysHQ/yosys.git
49 lines
969 B
Plaintext
49 lines
969 B
Plaintext
read_verilog <<EOT
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module wreduce_sub_test(input [3:0] i, input [7:0] j, output [8:0] o);
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assign o = (j >> 4) - i;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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design -save gold
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opt_expr
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wreduce
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select -assert-count 1 t:$sub r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
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design -stash gate
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design -import gold -as gold
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design -import gate -as gate
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -show-ports miter
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##########
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read_verilog <<EOT
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module wreduce_sub_signed_test(input signed [3:0] i, input signed [7:0] j, output signed [8:0] o);
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assign o = (j >>> 4) - i;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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design -save gold
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opt_expr
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wreduce
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dump
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select -assert-count 1 t:$sub r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
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design -stash gate
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design -import gold -as gold
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design -import gate -as gate
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -show-ports miter
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